Multi-protocol packet framing over an isochronous network
An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to cause incoming data to be deframed by the appropriate framer/deframer circuit depending on which slot of the network frame contained the information. Once deframed, a buffer manager controls storing of the information in a circular ring buffer in an external memory. A device residing on a host bus coupled to the integrated circuit may then read the information from the circular ring buffer via a parallel bus port of the integrated circuit. Information may also pass in the opposite direction from the parallel bus port, through a buffer memory port to the buffer memory, and from the buffer memory through the buffer memory port, through an appropriate framer/deframer circuit, through the isochronous network port, and onto the network.
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The microfiche appendix, which is a part of the present disclosure, entails one sheet of microfiche having a total of ninety-two (92) frames. The microfiche appendix contains RTL code and schematics of a specific embodiment of an integrated circuit in accordance with the present invention. A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
FIELD OF THE INVENTIONThis invention relates to isochronous networks.
BACKGROUND INFORMATIONEthernet is a well known network protocol. See the IEEE specification 802.3 (the subject matter of which is incorporated herein by reference) for further background information on Ethernet. Ethernet is well suited for transferring large packets of information at spaced intervals. Information may, for example, be accumulated into a large packet and then sent in a relatively large packet from one Ethernet node to another Ethernet node. Ethernet can therefore be said to be a “bursty” network protocol.
Some types of information, such as the information in a typical telephone conversation, do not lend themselves to being accumulated over time and then being transmitted as a single large packet. In a telephone conversation, speech information should be passed from speaker to listener without significant delay because the listener may use that speech information to formulate a response. Accordingly, there is not time for large packets of information to be accumulated. Frequent transmissions of small packets of information over the network is required. Ethernet is not well suited to this “nonbursty” type of information transfer.
There are, however, communication protocols (called isochronous protocols) which are suited for communication of such “nonbursty” information. Circuit switching and time division multiplexing (TDM) techniques are employed to divide a communication medium into a number of consecutive frames, each frame including a number of time slots. A first telephone conversation may, for example, be allocated a first slot of each frame whereas a second telephone conversation may be allocated a second slot of each frame. Because telephone information for each conversation is received each frame, the “nonbursty” information of the telephone conversations is communicated without significant delay.
Isochronous networks may also be made to carry “bursty” information. Telephone companies use an information framing protocol known as “HDLC” to frame information (“bursty” and/or “nonbursty”) for isochronous communication over a standard digital telephone line (an example of which is Primary Rate ISDN or “PRI”). HDLC is part of a more encompassing protocol called “X.25” See the document ISO/IEC 3309, 1991 (the subject matter of which is incorporated herein by reference) for additional information on the HDLC protocol.
“Bursty” information such as video information and large computer files, on the other hand, passes over another structure. A first Ethernet network 8 having a plurality of workstations and a file server and an Ethernet hub is coupled to a second Ethernet network 9 via two Ethernet lines 10, 11 and an Ethernet hub/router 12. The file server of a network may, for example, store video data which can be accessed and displayed by the workstations of the network. Lines 10 and 11 are logically two different Ethernet lines. Hub/router 12 is coupled to the central office/exchange 6 via an isochronous link 13 such as a PRI line. Information is passed over link 13 using the HDLC protocol. The dots on selected workstations indicate video cameras.
A video camera of a workstation in the first Ethernet network can therefore capture video information and store that information in the file server of the first Ethernet network 8. A workstation in the second Ethernet network 9 can then access that information over Ethernet lines 10 and 11 via hub/router 12 and display that information. A workstation can also receive HDLC packaged “bursty” information (such as the yellow pages in graphic form) from the central office/exchange 6 via isochronous link 13.
There exists, however, another information packaging protocol known as asynchronous transfer mode (hereinafter “ATM”). See the document “ATM User-Network Interface Specification”, Version 3.0 (the subject matter of which is incorporated herein by reference) for additional information on the ATM protocol. Although it is envisioned that ATM will eventually replace HDLC, it is likely that significant numbers of ATM and HDLC data communication services will coexist for a significant period of time. It would therefore be desirable to provide network node hardware capable of both ATM and HDLC communication. Furthermore, a user using the structure of
An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first protocol packet framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second protocol packet framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to steer incoming information to the appropriate packet framer/deframer circuit depending on which slot of the network frame carried the information.
In some embodiments, the information received from the network is stored in an external memory after being deframed. A buffer manager circuit may be provided on the integrated circuit to manage a circular inbound ring buffer of information in the external memory. A device, such as a CPU, residing on a host bus coupled to the integrated circuit may then read the information stored in the circular ring buffer via a parallel bus port of the integrated circuit. An arbiter circuit on the integrated circuit determines whether information from the framer/deframer circuit will be written to the external memory or whether the device on the host bus will read information from the external memory. In some embodiments, the integrated circuit includes a slot mapping memory which contains a map of which packet framer/deframer should be used for which slot. The slot mapping memory can be programmed from the host bus of the integrated circuit via the parallel bus port.
If information from the host bus is to be transmitted over the network, the information is written into the external buffer memory via the parallel bus port and the buffer memory port. The information is then framed by the appropriate packet framer/deframer circuit and is supplied to the isochronous network port of the integrated circuit via the circuit switch. The buffer manager circuit of the integrated circuit determines how the information is written into an outbound buffer of the external memory from the host parallel bus port and how that information is later read out of the outbound buffer and supplied to the packet framer/deframer circuit. The arbiter determines whether information received from the parallel bus port will be written into the external memory or whether information from the external memory will be supplied to the packet framer/deframer circuit for framing and transmission on the isochronous bus.
Other associated structures and methods are also disclosed.
An isochronous network specified by IEEE 802.9a (herein after referred to as “isoENET”) provides for transmission of both “nonbursty” and “bursty” information over a single Ethernet-compatible network. See the documents U.S. patent application Ser. No. 07/970,329 entitled “Frame-Based Transmission of Data”; IEEE specification 802.9a; and “IsoEnet Transforms LANs And WANs Into Interactive Multimedia Tools”, National Semiconductor Corporation, by Brian Edem et al., 1992 (the subject matter of all three documents is incorporated herein by reference) for further information on the IsoENET isochronous network.
In an isoENET network, the information being transmitted is broken up into a plurality of frames of information by a plurality of synchronization pulses. In addition to dedicated. Ethernet bandwidth, each frame contains 96 slots (also called “B-channels”). To transfer “bursty” information, multiple of these slots are filled with the bursty information. Several consecutive frames may be largely dedicated to the transfer of a burst of information whereas subsequent frames (after the burst) may carry no “bursty” information. To transfer “nonbursty” information, on the other hand, one slot of each successive frame may carry a small amount of “nonbursty” information. Accordingly, information from both a telephone and a workstation can be transferred over an isochronous network which is compatible with Ethernet.
Network 106 is an isoENET network which is capable of isochronous information transfer and is also compatible with the installed base of Ethernet networks. IsoENET network 106 includes four workstations 107-110, a telephone 111, and an isoENET hub 112. Because isoENET is capable of transmitting “nonbursty” telephone conversation information, telephone 111 is coupled to the isoENET network via workstation 107.
Video information (for example, MPEG encoded video) for display by the workstations of the two networks is stored in this example in a video server 113. Programs for use by the workstations of the two networks are stored in this example in a file server 114. The servers 113 and 114 are coupled to the two networks 100 and 106 via high speed 155 Mbps (megabits per second) fiber optic links 115-118 and an ATM switch 119. Accordingly, video information may be packaged in ATM format and transmitted from the video server 113 in “bursty” fashion over 155 Mbps link 118, 155 Mbps link 116, and isoENET line 107A to workstation 107.
A directory server 120 which supplies information in HDLC format may be provided by a telephone company. Directory server 120 is coupled to a central office/exchange 121 via a PRI line 122. The central office/exchange 121 is coupled to the ATM switch via a 155 Mbps link 123. Accordingly, information (such as yellow page graphic information) may be packaged in HDLC format and transmitted from the directory server 120 in “bursty” fashion over PRI line 122, 155 Mbps link 123, 155 Mbps link 116, and isoENET line 107A to workstation 107. Workstation 107 therefore is an isoENET node capable of communicating using both ATM and HDLC protocols. The structure of workstation 107 is described in further detail later.
Because network 100 is a standard Ethernet network which does not support “nonbursty” telephone conversation information, a telephone 124 associated with workstation 101 is not coupled to a workstation of network 100 but rather is coupled to a PBX 125 via a PBX line 126. Because network 106 is an isoENET network, telephone 111 transmits and receives “nonbursty” telephone conversation information via PBX-like line 127, isoENET line 107A, and PRI line 128. PBX 125 is coupled to the central office/exchange 121 via multiple PRI lines 129.
In
IsoENET line 107A of
To allow workstation 107 (see
Assume for illustrative purposes that isoENET frames are to be received from wires 205 of
After this initialization of the slot mapping memory 407, a channel counter (not shown) of circuit switch multiplexer/demultiplexer block 302 provides addresses to the receive portion of the slot mapping memory 407. Initially, the channel counter outputs a value which addresses the first memory location of the receive portion of memory 407. Because the first memory location of memory 407 was initialized to contain data which causes multiplexer/demultiplexer circuit 406 and HDLC packet framer/deframer circuit 404 to perform packet deframing, the first slot of the isoENET frame is deframed by HDLC packet framer/deframer circuit 404. After the information from the first slot is received, the channel counter is incremented. At the start of the second slot, the receive portion of memory 407 is read using the incremented count value output from the channel counter for the memory address. Because the second memory location of memory 407 was initialized to contain data which causes multiplexer/demultiplexer circuit 406 and ATM packet framer/deframer circuit 405 to perform packet deframing, the second slot of the isoENET frame is deframed by ATM packet framer/deframer circuit 405. After the information from the second slot is received, the channel counter is again incremented. Deframing of each successive slot of the isoENET frame proceeds in like fashion. The channel counter is reset by the rising edge of the frame synchronization signal received on wires 205 at the end of the frame. As an incoming packet is deframed, it is stored in a dedicated location in buffer 210.
When information is being written into buffer RAM 210 from one of the packet framer/deframer circuits, a buffer manager in block 408 of the integrated circuit determines where in memory 210 that information is written so that a separate receive ring buffer is maintained in memory 210 for each packet framer/deframer. The location and size of each ring buffer is set from the ISA bus by writing control registers in block 408. Four control registers are associated with each packet framer/deframer circuit: a control register defining the beginning location of the ring buffer in physical memory 210, a control register defining the ending location of the ring buffer in physical memory 210, a control register defining where in memory 210 the next incoming packet is to be written, and a control register defining where in memory 210 the oldest packet unread by the CPU is located. After an entire packet has been received and deframed by the appropriate packet framer/deframer circuit, the CPU is signalled via the ISA bus 201 that packet reception is complete. The CPU can then commence in the transfer of the packet data stored in buffer 210 to system memory via the ISA bus 201.
The block 408 actually includes two independent buffer managers. Each buffer manager is coupled to an associated packet framer/deframer circuit. Two HDLC packet framer/deframer circuits 403 and 404 are provided in the specific embodiment in order to support a specific video conferencing method. The present invention is not, however, limited to require two packet framer/deframers for the same protocol.
In some embodiments, block 408 also includes circuitry for managing a “receive cell buffer” in memory 210. The receive cell buffer can be used as a receptacle for ATM cells (a “cell” is an ATM construct and is 53 bytes of ATM information). When an ATM cell is received that is not part of a packet of information being written into a receive ring buffer, the ATM cell may be stored in the receive cell buffer. These stored ATM cells can then be accessed later via the ISA bus 201. Such ATM cells may, for example, be intermittently transmitted ATM cells which indicate the status of a conference call when the conversation of the conference call itself is being written into a receive ring buffer in memory 210. The receive cell buffer makes use of hardware in an ATM packet framer/deframer circuit which identifies cells from raw incoming data but does not utilize the higher level deframing hardware which identifies, packets of cells.
IsoBuffer integrated circuit 209 also includes a constant bit rate (CBR) buffer manager block 410 which manages raw unframed or nondeframed streams of data. The CBR buffer manager 410 keeps track of where a stream of raw data is being written into memory 210 by tracking frames (frames usually are transmitted at a 8 kHz rate) rather than by tracking the beginning and ending of packets. Given the number of bytes in a frame, and the starting location in memory 210, CBR buffer manager 410 can determine from the number of frames received the location at which raw nondeframed information is being written into memory 210. Nondeframed data in memory 210 may be deframed later in software by a CPU coupled to ISA bus 201. This constant bit rate buffer feature may be used to support a high level protocol which is not supported in hardware on integrated circuit 209 by a dedicated packet framer/deframer circuit.
Arbiter 409 determines which of the ISA bus 201, the buffer managers in block 408, or the CBR buffer manager 410 will have access to the buffer RAM 210. Any number of arbiter circuits can be used for this purpose. In one embodiment, each of the blocks 408, 410 and an ISA bus interface 411 provides a request signal on its own dedicated request line to the arbiter 409.
The microfiche appendix contains RTL code and schematics describing a specific embodiment of an integrated circuit which is described in block diagram form by
Although the invention is described in connection with certain illustrative embodiments for instructional purposes, the invention is not limited thereto. In some embodiments, the buffer memory is disposed on the same integrated circuit as the packet framer/deframer circuits and the circuit switch multiplexer/demultiplexer. Buses other than the ISA bus can be supported including the PCI bus and the Apple NuBUS. Accordingly, modifications, adaptations, and combinations of various aspects of the specific embodiments can be practiced without departing from the scope of the invention as set forth in the following claims.
Claims
1. An integrated circuit, comprising:
- an isochronous network port;
- a first protocol packet framer/deframer circuit;
- a second protocol packet framer/deframer circuit; and
- a circuit switch multiplexer/demultiplexer coupled to said isochronous network port, said first protocol packet framer/deframer circuit, and said second protocol packet framer/deframer circuit, wherein said circuit switch multiplexer/demultiplexer comprises a multiplexer/demultiplexer, and a storage device, said multiplexer/demultiplexer being at least in part controlled based on a value output from said storage device.
2. The integrated circuit of claim 1, wherein a plurality of isochronous frames are received on said isochronous network port, each of said isochronous frames comprising a plurality of slots, a first of said slots of a frame being supplied to and deframed by said first protocol packet framer/deframer circuit, a second of said slots of said frame being supplied to and deframed by said second protocol packet framer/deframer circuit.
3. The integrated circuit of claim 1, wherein said first protocol packet framer/deframer circuit deframes ATM formatted slots, and wherein said second protocol packet framer/deframer circuit deframes HDLC formatted slots.
4. The integrated circuit of claim 3, wherein said first protocol packet framer/deframer circuit deframes ATM cells.
5. The integrated circuit of claim 3, wherein said first protocol packet framer/deframer circuit deframes both ATM cells and ATM packets.
6. The integrated circuit of claim 1, wherein said storage device comprises a plurality of memory locations, and wherein said circuit switch multiplexer/demultiplexer further comprises:
- a receive counter, said receive counter being incremented after a receipt of a slot of information received on said isochronous network port, a count value output from said receive counter pointing to a corresponding memory location of said plurality of memory locations of said storage device.
7. The integrated circuit of claim 1, further comprising:
- a parallel bus port, said storage device being accessible from said parallel bus port.
8. The integrated circuit of claim 1, further comprising:
- a parallel bus port;
- parallel bus interface circuitry coupled to said parallel bus port;
- a memory; and
- an arbiter circuit coupled to said parallel bus interface circuitry and to said memory, said arbiter arbitrating access to said memory.
9. The integrated circuit of claim 8, further comprising:
- a buffer manager circuit coupled to said first protocol packet framer/deframer circuit, said second protocol packet framer/deframer circuit and to said arbiter circuit, said buffer manager circuit comprising: first and second receive pointer registers for pointing to a receive buffer in said memory; and first and second transmit pointer registers for pointing to a transmit buffer in said memory.
10. The integrated circuit of claim 8, further comprising:
- means, coupled to said circuit switch multiplexer/demultiplexer, for managing buffering of substantially nondeframed isochronous network data in said memory.
11. A method, comprising:
- deframing information of a slot of a frame of network information using a first protocol packet deframer circuit;
- deframing information of another slot of said frame of network information using a second protocol packet deframer circuit, said first and second protocol packet deframer circuits both being disposed on the same integrated circuit;
- incrementing a counter of said integrated circuit so that a count value output from said counter corresponds with a slot number of the slot being received into said integrated circuit; and
- using said count value to address a slot mapping memory of said integrated circuit.
12. The method of claim 11, wherein said integrated circuit has a parallel bus port, said method further comprising:
- programming said slot mapping memory of said integrated circuit via said parallel bus port.
13. The method of claim 11, further comprising:
- storing information deframed by said first protocol packet deframer circuit in a first ring buffer; and
- storing information deframed by said second protocol packet deframer circuit in a second ring buffer.
14. An integrated circuit, comprising:
- a first packet deframer circuit which deframes information in accordance with a first network protocol;
- a second packet deframer circuit which deframes information in accordance with a second network protocol; and
- means for causing said first packet deframer circuit to deframe information in a first isochronous network slot of a frame in accordance with said first network protocol and for causing said second packet deframer circuit to deframe information in a second isochronous network slot of said frame in accordance with said second network protocol, wherein said means comprises means for storing slot mapping information.
15. The integrated circuit of claim 14, wherein said first network protocol is an ATM protocol and wherein said second network protocol is an HDLC protocol.
16. An integrated circuit comprising:
- a first packet deframer circuit which deframes information in accordance with a first network protocol;
- a second packet deframer circuit which deframes information in accordance with a second network protocol;
- means for causing said first packet deframer circuit to deframe information in a first isochronous network slot of a frame in accordance with said first network protocol and for causing said second packet deframer circuit to deframe information in a second isochronous network slot of said frame in accordance with said second network protocol;
- means for managing a receive ring buffer;
- a parallel bus port; and
- parallel bus interface circuitry coupled to said parallel bus port.
17. The integrated circuit of claim 14, further comprising:
- a first packet framer circuit which frames information in accordance with a network protocol; and
- a second packet framer circuit which frames information in accordance with a network protocol,
- wherein said means for causing comprises: a multiplexer having a first input lead, a second input lead, and an output lead, said first input lead being coupled to an output lead of said first packet framer circuit, said second input lead being coupled to an output lead of said second packet framer circuit, and an output lead being coupled to an output part of an isochronous network port of said integrated circuit; and a demultiplexer having an input lead, a first output lead, and a second output lead, said input lead being coupled to an input part of said isochronous network port, said first output lead being coupled to an input lead of said first packet deframer circuit, and said second output lead being coupled to an input lead of said second packet deframer circuit.
18. An integrated circuit, comprising:
- an isochronous network port, wherein the isochronous network port receives frame of information, said frame having a plurality of non-isochronous and isochronous slots, and each of said isochronous slots having information of one of at least a first protocol or a second protocol;
- a first protocol packet framer/deframer circuit;
- a second protocol packet framer/deframer circuit; and
- a circuit switch multiplexer/demultiplexer coupled to said isochronous network port, said first protocol packet framer/deframer circuit, and said second protocol packet framer/deframer circuit, wherein the circuit switch multiplexer/demultiplexer couples said isochronous first protocol slots to the first protocol packet framer/deframer circuit and couples said isochronous second protocol slots to the second protocol packet framer/deframer circuit.
19. The integrated circuit of claim 18 further comprising:
- a first demultiplexer coupled to said isochronous network port, wherein the first demultiplexer separates the non-isochronous slots from the isochronous slots, and the circuit switch multiplexer/demultiplexer is coupled to the first demultiplexer.
20. The integrated circuit of claim 18, wherein said circuit switch multiplexer/demultiplexer comprises:
- a multiplexer/demultiplexer; and
- a storage device, said multiplexer/demultiplexer being at least in part controlled based on a value output from said storage device.
21. The integrated circuit of claim 18, wherein a plurality of isochronous slots are received on said isochronous network port, a first of said isochronous slots of a frame being provided to and deframed by said first protocol packet framer/deframer circuit, and a second of said isochronous slots of said frame being provided to and deframed by said second protocol packet framer/deframer circuit.
22. The integrated circuit of claim 18, wherein said first protocol packet framer/deframer circuit deframes ATM formatted slots, and wherein said second protocol packet framer/deframer circuit deframes HDLC formatted slots.
23. The integrated circuit of claim 22, wherein said first protocol packet framer/deframer circuit deframes ATM cells.
24. The integrated circuit of claim 22, wherein said first protocol packet framer/deframer circuit deframes both ATM cells and ATM packets.
25. The integrated circuit of claim 20, wherein said storage device comprises a plurality of memory locations, and wherein said circuit switch multiplexer/demultiplexer further comprises:
- a receive counter, said receive counter being incremented after a receipt of a slot of information received on said isochronous network port, a count value output from said receive counter pointing to a corresponding memory location of said plurality of memory locations of said storage device.
26. The integrated circuit of claim 20, further comprising:
- a parallel bus port, said storage device being accessible from said parallel bus port.
27. The integrated circuit of claim 20, further comprising:
- a parallel bus port;
- parallel bus interface circuitry coupled to said parallel bus port;
- a memory; and
- an arbiter circuit coupled to said parallel bus interface circuitry and to said memory, said arbiter arbitrating access to said memory.
28. The integrated circuit of claim 27, further comprising:
- a buffer manager circuit coupled to said first protocol packet framer/deframer circuit, said second protocol packet framer/deframer circuit and to said arbiter circuit, said buffer manager circuit comprising:
- first and second receive pointer registers for pointing to a receive buffer in said memory; and
- first and second transmit pointer registers for pointing to a transmit buffer in said memory.
29. The integrated circuit of claim 27, further comprising:
- means, coupled to said circuit switch multiplexer/demultiplexer, for managing buffering of substantially nondeframed isochronous network data in said memory.
30. A method, comprising:
- framing network information, wherein network information frames include non-isochronous and isochronous slots;
- deframing information of an isochronous slot of using a first protocol packet deframer circuit; and
- deframing information of another isochronous slot using a second protocol packet deframer circuit, said first and second protocol packet deframer circuits both being disposed on the same integrated circuit.
31. The integrated circuit of claim 30, wherein said first protocol packet framer/deframer circuit deframes ATM formatted slots, and wherein said second protocol packet framer/deframer circuit deframes HDLC formatted slots.
32. The method of claim 30 wherein each isochronous slot is formatted with at least one of a first protocol or a second protocol, the method further comprising the steps of:
- separating the non-isochronous slots from the isochronous slots into a non-isochronous data stream and an isochronous data stream;
- coupling the isochronous slots formatted with the first protocol to the first protocol packet deframer circuit; and
- coupling the isochronous slots formatted with the second protocol to the second protocol packet deframer circuit.
33. The method of claim 32 further comprising the step of:
- demultiplexing the isochronous slots; and
- wherein the separating step includes the step of demultiplexing with a first demultiplexer each network information frame.
34. The method of claim 30 further comprising the steps of:
- flaming information having a first protocol using a first protocol packet framer circuit;
- framing information having a second protocol using a second protocol packet framer circuit;
- combining the first protocol framed information and the second protocol framed information into isochronous slots; and
- combining isochronous slots with non-isochronous slots into a frame.
35. The method of claim 30, further comprising:
- incrementing a counter of said integrated circuit so that a count value output from said counter corresponds with a slot number of the slot being received into said integrated circuit; and using said count value to address a slot mapping memory of said integrated circuit.
36. The method of claim 35, wherein said integrated circuit has a parallel bus port, said method further comprising:
- programming said slot mapping memory of said integrated circuit via said parallel bus port.
37. The method of claim 35, further comprising:
- storing information deframed by said first protocol packet deframer circuit in a first ring buffer; and
- storing information deframed by said second protocol packet deframer circuit in a second ring buffer.
38. An integrated circuit, comprising:
- means for framing information, each information frame having isochronous and non-isochronous slots and each of said isochronous slots having information formatted by one of at least a first network protocol or a second network protocol;
- means for receiving the framed information;
- means for separating the isochronous slots and the non-isochronous slots;
- a first means for combining information formatted by a first protocol into a first packet;
- a second means for combining information formatted by a second protocol into a second packet; and
- means for coupling first protocol formatted information in an isochronous slot to the first means for combining and for coupling second protocol formatted information in another isochronous slot to the second means for combining.
39. The integrated circuit of claim 38 further comprising:
- a first means for separating a packet of information formatted by a first protocol into first segments of information;
- a second means for disassembling a packet of information formatted by a second protocol into second segments of information; and
- means for combining the first information segments and the second information segments into an isochronous data stream; means for combining the isochronous data stream with a non-isochronous data stream.
40. The integrated circuit as in claim 39 wherein the means for combining includes the step of inserting the first segments and the second segments into isochronous slots of a frame and non-isochronous data stream segments into non-isochronous slots of the frame.
41. The integrated circuit of claim 38, wherein said first network protocol is an ATM protocol and wherein said second network protocol is an HDLC protocol.
42. The integrated circuit of claim 38, wherein said means for coupling comprises means for storing slot mapping information.
43. The integrated circuit of claim 38, further comprising:
- means for managing a receive ring buffer;
- a parallel bus port; and
- parallel bus interface circuitry coupled to said parallel bus port.
44. The integrated circuit of claim 38, further comprising:
- a first packet framer circuit which frames information in accordance with a network protocol; and
- a second packet framer circuit which frames information in accordance with a network protocol,
- wherein said means for coupling comprises: a multiplexer having a first input lead, a second input lead, and an output lead, said first input lead being coupled to an output lead of said first packet framer circuit, said second input lead being coupled to an output lead of said second packet framer circuit, and an output lead being coupled to an output part of an isochronous network port of said integrated circuit; and
- a demultiplexer having an input lead, a first output lead, and a second output lead, said input lead being coupled to an input part of said isochronous network port, said first output lead being coupled to an input lead of said first packet deframer circuit, and said second output lead being coupled to an input lead of said second packet deframer circuit.
45. An apparatus, comprising:
- an isochronous port;
- one or more first protocol packet framer/deframer circuits;
- one or more second protocol packet framer/deframer circuits; and
- a circuit switch multiplexer/demultiplexer coupled to the isochronous port, at least one of the first protocol packet framer/deframer circuits, and at least one of the second protocol packet framer/deframer circuits, wherein the circuit switch multiplexer/demultiplexer comprises a multiplexer/demultiplexer and a storage device, the multiplexer/demultiplexer being at least in part controlled based on an output from the storage device.
46. The apparatus of claim 45, wherein the isochronous port comprises a time division multiplexed port.
47. An apparatus, comprising:
- an isochronous port;
- a first protocol circuit;
- a second protocol circuit; and
- a circuit switch multiplexer/demultiplexer coupled to the isochronous port, the first protocol circuit, and the second protocol circuit, wherein the circuit switch multiplexer/demultiplexer comprises a multiplexer/demultiplexer and a storage device, the multiplexer/demultiplexer being at least in part controlled based on an output from the storage device.
48. The apparatus of claim 47, wherein the first protocol circuit manages raw data.
49. The apparatus of claim 47, wherein the first protocol circuit manages unframed data.
50. The apparatus of claim 47, wherein the first protocol circuit manages nondeframed data.
51. The apparatus of claim 47, wherein the first protocol circuit comprises a constant bit rate buffer circuit.
52. The apparatus of claim 47, wherein the second protocol circuit comprises a packet framer/deframer circuit.
53. The apparatus of claim 47, wherein the second protocol circuit comprises an HDLC framer/deframer circuit.
54. The apparatus of claim 47, wherein the second protocol circuit comprises multiple packet framer/deframer circuits.
55. The apparatus of claim 47, wherein the second protocol circuit comprises multiple HDLC framer/deframer circuits.
56. The apparatus of claim 47, wherein the second protocol circuit comprises an asynchronous transfer mode framer/deframer circuit.
57. The apparatus of claim 47, wherein the isochronous port comprises a time division multiplexed port.
58. An apparatus, comprising:
- an isochronous port;
- one or more first protocol circuits;
- one or more second protocol circuits;
- a circuit switch multiplexer/demultiplexer coupled to the isochronous port, at least one of the first protocol circuits, and at least one of the second protocol circuits, wherein the circuit switch multiplexer/demultiplexer comprises a multiplexer/demultiplexer and a storage device, the multiplexer/demultiplexer being at least in part controlled based on an output from the storage device; and
- a buffer memory, wherein a signal path is provided from the isochronous port to at least one of the first protocol circuits, and from the at least one first protocol circuit to the buffer memory, and from the buffer memory to at least one of the second protocol circuits, and from the second protocol circuit to the isochronous port.
59. The apparatus of claim 58, wherein at least one of the first protocol circuit manages raw data.
60. The apparatus of claim 58, wherein at least one of the first protocol circuit manages unframed data.
61. The apparatus of claim 58, wherein the first protocol circuit manages nondeframed data.
62. The apparatus of claim 58, wherein the first protocol circuit comprises a constant bit rate buffer circuit.
63. The apparatus of claim 58, wherein the second protocol circuit comprises a packet framer/deframer circuit.
64. The apparatus of claim 58, wherein the second protocol circuit comprises an HDLC framer/deframer circuit.
65. The apparatus of claim 58, wherein the second protocol circuit comprises multiple packet framer/deframer circuits.
66. The apparatus of claim 58, wherein the second protocol circuit comprises multiple HDLC framer/deframer circuits.
67. The apparatus of claim 58, wherein the second protocol circuit comprises an asynchronous transfer mode framer/deframer circuit.
68. The apparatus of claim 58, wherein the isochronous port comprises a time division multiplexed port.
69. A method, comprising:
- deframing information of a received slot of information using a first protocol packet deframer circuit;
- deframing information of another received slot of information using a second protocol packet deframer circuit;
- generating an output that corresponds with the slot being received; and
- using the output to address a slot mapping memory.
70. An apparatus, comprising:
- a first packet deframer circuit which deframes information in accordance with a first protocol;
- a second packet deframer circuit which deframes information in accordance with a second protocol; and
- means for causing the first packet deframer circuit to deframe information in a first isochronous slot of a frame in accordance with the first protocol and for causing the second packet deframer circuit to deframe information in a second isochronous slot of the frame in accordance with the second protocol, wherein the means comprises means for storing slot mapping information.
71. An apparatus comprising:
- a first packet deframer circuit which deframes information in accordance with a first protocol;
- a second packet deframer circuit which deframes information in accordance with a second protocol;
- means for causing the first packet deframer circuit to deframe information in a first isochronous slot of a frame in accordance with the first protocol and for causing the second packet deframer circuit to deframe information in a second isochronous slot of the frame in accordance with the second protocol;
- means for managing a receive buffer;
- a port; and
- interface circuitry coupled to the port.
72. An apparatus comprising:
- a first packet deframer circuit which deframes information in accordance with a first protocol;
- a second packet deframer circuit which deframes information in accordance with a second protocol;
- means for causing the first packet deframer circuit to deframe information in a first isochronous slot of a frame in accordance with the first network protocol and for causing the second packet deframer circuit to deframe information in a second isochronous slot of the frame in accordance with the second protocol;
- means for managing a receive buffer;
- a bus port for coupling to a bus; and
- interface circuitry coupled to the bus port, wherein the bus supports multiple transfer types, such as direct memory access, shared memory access or standard I/O access.
73. An apparatus, comprising:
- an isochronous port, wherein the isochronous port receives a frame of information, the frame having a plurality of non-isochronous and isochronous slots, and each of the isochronous slots having information of one of at least a first protocol or a second protocol;
- a first protocol packet framer/deframer circuit;
- a second protocol packet framer/deframer circuit; and
- a circuit switch multiplexer/demultiplexer coupled to the isochronous port, the first protocol packet framer/deframer circuit, and the second protocol packet framer/deframer circuit, wherein the circuit switch multiplexer/demultiplexer couples the isochronous first protocol slots to the first protocol packet framer/deframer circuit and couples the isochronous second protocol slots to the second protocol packet framer/deframer circuit.
74. A method, comprising:
- framing information, wherein information frames include non-isochronous and isochronous slots;
- deframing information of an isochronous slot of using a first protocol packet deframer circuit; and
- deframing information of another isochronous slot using a second protocol packet deframer circuit, said first and second protocol packet deframer circuits being coupled to a common buffer memory.
75. An apparatus, comprising:
- means for framing information, each information frame having isochronous and non-isochronous slots and each of the isochronous slots having information formatted by one of at least a first protocol or a second protocol;
- means for receiving the framed information;
- means for separating the isochronous slots and the non-isochronous slots;
- a first means for combining information formatted by a first protocol into a first packet;
- a second means for combining information formatted by a second protocol into a second packet; and
- means for coupling first protocol formatted information in an isochronous slot to the first means for combining and for coupling second protocol formatted information in another isochronous slot to the second means for combining.
76. An apparatus comprising:
- a network port;
- a multiplexer/demultiplexer circuit coupled to the network port;
- a first protocol circuit and a second protocol circuit each coupled to the multiplexer/demultiplexer circuit; and
- a buffer coupled to the first and second protocol circuit;
- wherein a signal path is provided from the network port to the first protocol circuit, and from the first protocol circuit to the buffer, and from the buffer to the second protocol circuit, and from the second protocol circuit to the network port.
77. The apparatus of claim 76, wherein the first protocol circuit manages raw data.
78. The apparatus of claim 76, wherein the first protocol circuit manages unframed data.
79. The apparatus of claim 76, wherein the first protocol circuit manages nondeframed data.
80. The apparatus of claim 76, wherein the first protocol circuit comprises a constant bit rate buffer circuit.
81. The apparatus of claim 76, wherein the second protocol circuit comprises a packet framer/deframer circuit.
82. The apparatus of claim 76, wherein the second protocol circuit comprises an HDLC framer/deframer circuit.
83. The apparatus of claim 76, wherein the second protocol circuit comprises multiple packet framer/deframer circuits.
84. The apparatus of claim 76, wherein the second protocol circuit comprises multiple HDLC framer/deframer circuits.
85. The apparatus of claim 76, wherein the second protocol circuit comprises an asynchronous transfer mode framer/deframer circuit.
86. The apparatus of claim 76, wherein the network port comprises a time division multiplexed port.
87. A method comprising:
- coupling information from a network to an isochronous port, the information including non-isochronous and isochronous slots;
- coupling the information from the isochronous port to a multiplexer/demultiplexer;
- selectively coupling the information from the multiplexer/demultiplexer to a first protocol circuit and a second protocol circuit; and
- selectively coupling the information from/to the first and second protocol circuit to a buffer;
- wherein a signal path is provided from the isochronous port to the first protocol circuit, and from the first protocol circuit to the buffer, and from the buffer to the second protocol circuit, and from the second protocol circuit to the isochronous port.
88. The method of claim 87, wherein the first protocol circuit manages raw data.
89. The method of claim 87, wherein the first protocol circuit manages unframed data.
90. The method of claim 87, wherein the first protocol circuit manages nondeframed data.
91. The method of claim 87, wherein the first protocol circuit comprises a constant bit rate buffer circuit.
92. The method of claim 87, wherein the second protocol circuit comprises a packet framer/deframer circuit.
93. The method of claim 87, wherein the second protocol circuit comprises an HDLC framer/deframer circuit.
94. The method of claim 87, wherein the second protocol circuit comprises multiple packet framer/deframer circuits.
95. The method of claim 87, wherein the second protocol circuit comprises multiple HDLC framer/deframer circuits.
96. The method of claim 87, wherein the second protocol circuit comprises an asynchronous transfer mode framer/deframer circuit.
97. The method of claim 87, wherein the network port comprises a time division multiplexed port.
3619505 | November 1971 | Melle |
3835260 | September 1974 | Prescher et al. |
3988716 | October 26, 1976 | Fletcher et al. |
4150404 | April 17, 1979 | Tercic et al. |
4220816 | September 2, 1980 | Howells et al. |
4258434 | March 24, 1981 | Glowinski et al. |
4347527 | August 31, 1982 | Lainez |
4359770 | November 16, 1982 | Suzuka |
4412324 | October 25, 1983 | Glowinsky et al. |
4419765 | December 6, 1983 | Wycoff et al. |
4429405 | January 31, 1984 | Bux et al. |
4445213 | April 24, 1984 | Baugh et al. |
4449248 | May 15, 1984 | Leslie et al. |
4472802 | September 18, 1984 | Pin et al. |
4484218 | November 20, 1984 | Boland et al. |
4530088 | July 16, 1985 | Hamstra et al. |
4543652 | September 24, 1985 | Amada et al. |
4547880 | October 15, 1985 | De Vita et al. |
4549292 | October 22, 1985 | Isaman et al. |
4556970 | December 3, 1985 | Flanagin et al. |
4577312 | March 18, 1986 | Nash |
4577315 | March 18, 1986 | Otsuka |
4580276 | April 1, 1986 | Andruzzi, Jr. et al. |
4587650 | May 6, 1986 | Bell |
4637014 | January 13, 1987 | Bell et al. |
4656592 | April 7, 1987 | Spaanenburg et al. |
4674082 | June 16, 1987 | Flanagin et al. |
4677611 | June 30, 1987 | Yanosy, Jr. et al. |
4715002 | December 22, 1987 | Vernon et al. |
4726018 | February 16, 1988 | Bux et al. |
4759010 | July 19, 1988 | Murata et al. |
4766590 | August 23, 1988 | Hamada et al. |
4766591 | August 23, 1988 | Huang |
4769813 | September 6, 1988 | Lenart |
4771417 | September 13, 1988 | Maxwell et al. |
4771426 | September 13, 1988 | Rattlingourd et al. |
4782485 | November 1, 1988 | Gollub |
4800560 | January 24, 1989 | Aoki et al. |
4807224 | February 21, 1989 | Naron et al. |
4811367 | March 7, 1989 | Tajika |
4825435 | April 25, 1989 | Admundsen et al. |
4837799 | June 6, 1989 | Prohs et al. |
4845609 | July 4, 1989 | Lighthart et al. |
4847613 | July 11, 1989 | Sakurai et al. |
4858232 | August 15, 1989 | Diaz et al. |
4866704 | September 12, 1989 | Bergman |
4872157 | October 3, 1989 | Hemmady et al. |
4876683 | October 24, 1989 | Suzuki |
4897831 | January 30, 1990 | Negi et al. |
4907260 | March 6, 1990 | Prohs et al. |
4920483 | April 24, 1990 | Pogue et al. |
4930127 | May 29, 1990 | Abaziou et al. |
4931250 | June 5, 1990 | Greszczuk |
4954988 | September 4, 1990 | Robb |
4959774 | September 25, 1990 | Davis |
4961188 | October 2, 1990 | Lau |
4964121 | October 16, 1990 | Moore |
4977582 | December 11, 1990 | Nichols et al. |
4985891 | January 15, 1991 | Fujiwara et al. |
4993026 | February 12, 1991 | Yamashita |
5001707 | March 19, 1991 | Kositpaiboon et al. |
5007045 | April 9, 1991 | Tsuzuki |
5014247 | May 7, 1991 | Albachten, III et al. |
5018136 | May 21, 1991 | Gollub |
5020058 | May 28, 1991 | Holden et al. |
5020132 | May 28, 1991 | Nazarenko et al. |
5041924 | August 20, 1991 | Blackborow et al. |
5058110 | October 15, 1991 | Beach et al. |
5065398 | November 12, 1991 | Takashima |
5067149 | November 19, 1991 | Schneid et al. |
5084872 | January 28, 1992 | Le Cucq et al. |
5095494 | March 10, 1992 | Takahashi et al. |
5103446 | April 7, 1992 | Fischer |
5119373 | June 2, 1992 | Fredricsson et al. |
5121382 | June 9, 1992 | Yang et al. |
5128930 | July 7, 1992 | Nazarenko et al. |
5134611 | July 28, 1992 | Steinka et al. |
5138440 | August 11, 1992 | Radice |
5140587 | August 18, 1992 | Mueller et al. |
5146455 | September 8, 1992 | Goke et al. |
5163148 | November 10, 1992 | Walls |
5164938 | November 17, 1992 | Jurkevich et al. |
5179554 | January 12, 1993 | Lomicka et al. |
5189414 | February 23, 1993 | Tawara |
5200952 | April 6, 1993 | Bernstein et al. |
5202899 | April 13, 1993 | Walsh |
5206863 | April 27, 1993 | Nazarenko et al. |
5208807 | May 4, 1993 | Gass et al. |
5212724 | May 18, 1993 | Nazarenko et al. |
5214648 | May 25, 1993 | Lespagnol et al. |
5229998 | July 20, 1993 | Weisser |
5251207 | October 5, 1993 | Abensour et al. |
5283786 | February 1, 1994 | Hoff et al. |
5305306 | April 19, 1994 | Spinney et al. |
5305317 | April 19, 1994 | Szczepanek |
5311114 | May 10, 1994 | Sambamurthy et al. |
5315588 | May 24, 1994 | Kajiwara et al. |
5361261 | November 1, 1994 | Edem et al. |
5375121 | December 20, 1994 | Nishino et al. |
5410535 | April 25, 1995 | Yang et al. |
5453984 | September 26, 1995 | Mueller |
5504738 | April 2, 1996 | Sambamurthy et al. |
5533018 | July 2, 1996 | DeJager et al. |
5594734 | January 14, 1997 | Worsley et al. |
5648956 | July 15, 1997 | Sambamurthy et al. |
5761292 | June 2, 1998 | Wagner et al. |
0131662 | January 1985 | EP |
0318332 | May 1989 | EP |
A1254035 | October 1989 | JP |
A1297926 | December 1989 | JP |
A5175977 | July 1993 | JP |
WOA88055233 | July 1988 | WO |
WOA8911183 | November 1989 | WO |
- U.S. Appl. No. 07/969,916 filed Nov. 1992 to Edem et al.
- “ISO/IEC 3309” International Standard, reference No. ISO/IEC 3309:1991(E), 1991 6 pgs.
- “ATM User-Network Interface Specification: Version 3.0”, Technical Committee of the ATM Forum, pp. iii-103.
- “IEEE Standards For Local & Metropolitan Area Networks”, Prepared by IEEE 802.9a Editor, unapproved IEEE Standards Draft, Jul. 25, 1994, pp. i-289.
- A disclosure of a communication system was presented at the IEEE 802.9, Standards Meeting on Nov. 8-12, 1992. The pages entitled: “Multi-Media Applications are Ready”.
- “ATM Overview,” National Semiconductor Corp., ATM Overview F-Fred Device, Aug. 1993, entire booklet.
- “DP839XX Isochronous Time Slot Exchanger (IsoTSX™),” Revision 0.8, bearing the date Oct. 29, 1992 and DP839XX Isochronous Ethernet Physical Layer isoPHY™ Revision 1.1, bearing the date Oct. 1992, were disclosed to IBM.
- DP839XX Isochronous Ethernet Physical Layer Iso-PHY™, Revision 2.1, bearing the date Dec. 1992 and DP839XX Isochronous Time Slot Exchanger, Revision 1.0, bearing the date Dec. 13, 1992, were disclosed to IBM and Ericsson.
- DP839XX Isochronous Ethernet Physical Layer Iso-PHY™, Revision 3.0, bearing the date Dec. 1992 and Isochronous Time Slot Exchanger (IsoTSX™ Workbook, Revision 1.2, bearing the date Feb. 16, 1993, was disclosed to Luxcom, Inc. of Fremont, California.
- “DP8390 Network Interface Controller: An Introductory Guide”, Local Area Network Databook, National Semiconductor Corp., pp. 1-206 to 1-213, 1992 Edition.
- “DP83950A Repeater Interface Controller,” Local Area Network Databook, National Semiconductor Corp., pp. 3-3 to 3-73, 1992 Edition.
- DP83950EB at IEEE 802.3, Multi-Port Repeater Evaluation Kit, Local Area Network Databook, National Semiconductor Corp., pp. 75-87, 1992 Edition.
- “DP83932B Systems-Oriented Network Interface Controller”, Local Area Network Databook, National Semiconductor Corp., pp. 1-288 to 1-383, 1992 Edition.
- “Exchangeable Card Architecture Specification,” Release 1.00, bearing the date Dec. 20, 1991, pp. 7, 20 and 22.
- “Fiber Distributed Data Interface (FDDI)—Token Ring Media Access Control (MAC),” American National Standard for Information System—Document ANSI X3.139, 1987.
- Gallagher, C.A., “IEEE 802.9: A Multi-Service Lan Interface,” Second IEEE National Conference on Telecommunications, Apr. 1989, York GB, pp. 173-178.
- HMUX ERS “FDDI-II Hybrid Multiplexor (HMUX),” Rev. 2.4, Mar. 25, 1991.
- IBM—On or about Nov. 1, 1991, IBM Corporation provided a “Task Order and appendix”. A copy of pp. 6 and 7 of the Task Order and appendix titled, Isoethernet Project Local Cluster Controller Version 1.2.
- “IBM's Multimedia Venture: Oppurtunity for its Hardware?,” vol. 38, No. 1930, p. 1, Sep. 21, 1992.
- “IEEE 802.3, Draft Supplement to IEEE Std 802.3 DSMA/CD Access Method and Physical Layer Specifications,” Institute of Electrical and Electronics, Nov. 15, 1989.
- “IEEE 802.9, Draft Standard Integrated Services (IS) LAN Interface at the MAC and PHY Layers,” Institute of Electrical and Electronics, Nov. 1992.
- “Integrated PBX Systems, An NCC State of the Art Report,” The National Computer Centre Limited, 1987.
- Irube et al., “Integrated Information and Communication System for Business Networks,” Hitachi Review 40(3):241-247, 1991.
- “ISDN Basic Rate Interface System Design Guide,” Telenetworks document, Aug. 1989.
- “ISDN Primary Rate Interface System Design Guide,” Telenetworks document, Jul. 1989.
- “IsoEnet Transforms LANs and WANs Into Interactive Multimedia Tools,” Brian Edem et al., Computer Technology Review, Winter 1992, 3 pgs. “ISO/IEC 3309” International Standard, ref. No. ISO/IEC 3309; 1991 (E), 1991, 7 pgs.
- “Local Area Network Databook” published by National Semiconductor, pp. 1-3 to 1-9, 1-242 to 1-248, 5-3 to 5-7.
- Martini et al., “Real-Time Traffic in FDDI-II, Packet Switching vs. Circuit Switching,” IEEE Infocom 1991, vol. 3, Apr. 1991, Bal Harbour, U.S., pp. 1413-1420.
- “National Proposes Isochronous Ethernet,” Electronic News, vol. 38, No. 1940, p. 19, Nov. 30, 1992.
- “PCMCIA Socket Services Interface Specification,” Draft 2.00b, bearing the date Jul. 17, 1992.
- Ross, F.E. et al., FDDI—A Lan Among Mans, Computer Communications Review, vol. 20, No. 3, Jul. 1990, New York, U.S., pp. 16-31.
- Shimizu, H. et al., “IVDLAN Standardization and Development,” IEICE Transactions, vol. E74, No. 9, Sep. 1991, Tokyo, JP, pp. 2696-2702.
- “Token-Ring Network Architecture Reference,” pp. 5-1 through 5-28 and pp. 5-10 and 5-17.
- “VersaNet™ An Ethernet Extension for Isochronous Communications,” bearing the date Aug. 14, 1992 is a paper sent to National Semiconductor Corp. from Condor Systems, Inc. of San Jose, CA on Aug. 18, 1992.
- Wirbel, Loring, “Scheme for Fast Ethernet Proposed,” appears to be a newspaper article; date of article is uncertain, but is believed to be prior to Mar. 1993.
- Wong, David., “Second Generation 10Base T Silicon Solutions,” IRE Wescon Convention Record, vol. 35, Nov. 1991, No. Hollywood, Ca. pp. 238-242.
Type: Grant
Filed: Jul 2, 1998
Date of Patent: Oct 11, 2005
Assignee: Negotiated Data Solutions LLC (Chicago, IL)
Inventors: Gregory L. Dejager (San Jose, CA), Erik R. Swenson (San Jose, CA)
Primary Examiner: Salvatore Cangialosi
Attorney: Loudermilk & Associates
Application Number: 09/285,303