Patents by Inventor Gregory M. Nordstrom

Gregory M. Nordstrom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10838816
    Abstract: A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Timothy R. Block, Christoper J. Engel, Kaveh Naderi, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand
  • Patent number: 10417166
    Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.
    Type: Grant
    Filed: November 25, 2017
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
  • Patent number: 10417167
    Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.
    Type: Grant
    Filed: November 25, 2017
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
  • Patent number: 10169287
    Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Johns, Andrew T. Koch, Gregory M. Nordstrom
  • Patent number: 10031769
    Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Srinivas Kotta, Gregory M. Nordstrom, Timothy J. Schimke
  • Patent number: 10025616
    Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Srinivas Kotta, Gregory M. Nordstrom, Timothy J. Schimke
  • Publication number: 20180081761
    Abstract: A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Timothy R. Block, Christoper J. Engel, Kaveh Naderi, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand
  • Publication number: 20180074993
    Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.
    Type: Application
    Filed: November 25, 2017
    Publication date: March 15, 2018
    Inventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
  • Publication number: 20180074992
    Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.
    Type: Application
    Filed: November 25, 2017
    Publication date: March 15, 2018
    Inventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
  • Publication number: 20180052801
    Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 22, 2018
    Inventors: Charles R. Johns, Andrew T. Koch, Gregory M. Nordstrom
  • Patent number: 9891998
    Abstract: A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Timothy R. Block, Christopher J. Engel, Kaveh Naderi, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand
  • Patent number: 9870335
    Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
  • Patent number: 9870336
    Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
  • Publication number: 20180004566
    Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Inventors: Jesse P. Arroyo, Srinivas Kotta, Gregory M. Nordstrom, Timothy J. Schimke
  • Publication number: 20180004565
    Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Inventors: Jesse P. Arroyo, Srinivas Kotta, Gregory M. Nordstrom, Timothy J. Schimke
  • Patent number: 9842081
    Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: December 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Johns, Andrew T. Koch, Gregory M. Nordstrom
  • Patent number: 9811498
    Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Johns, Andrew T. Koch, Gregory M. Nordstrom
  • Patent number: 9766916
    Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Srinivas Kotta, Gregory M. Nordstrom, Timothy J. Schimke
  • Patent number: 9697155
    Abstract: A method, system and computer program product are provided for detecting and configuring an external input/output (IO) enclosure in a computer system. A PCIE Host Bridge (PHB) in a system unit is connected to a plurality of PCIE add-in card slots. One or more cables are connected between the PHB and the external enclosure. System firmware including detecting and configuring functions uses sideband structure for detecting a PCIE cable card and configuring the external input/output (IO) enclosure.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Curtis S. Eide, Christopher J. Engel, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand, William A. Thompson
  • Patent number: 9697156
    Abstract: A method, system and computer program product are provided for detecting and configuring an external input/output (IO) enclosure in a computer system. A PCIE Host Bridge (PHB) in a system unit is connected to a plurality of PCIE add-in card slots. One or more cables are connected between the PHB and the external enclosure. System firmware including detecting and configuring functions uses sideband structure for detecting a PCIE cable card and configuring the external input/output (IO) enclosure.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Curtis S. Eide, Christopher J. Engel, Gregory M. Nordstrom, Harald Pross, Thomas R. Sand, William A. Thompson