Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.

Abstract: Subject matter disclosed herein may relate to devices formed from correlated electron material.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters. In embodiments, CEM devices fabricated at a first stage of a wafer fabrication process, such as a front-end-of-line stage, may differ from CEM devices fabricated at a second stage of a wafer fabrication process, such as a middle-of-line stage or a back-end-of-line stage, for example.

Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.

Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.

Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) device. In embodiments, after formation of the one or more CEM traces, a spacer may be deposited in contact with the one or more CEM traces. The spacer may operate to control an atomic concentration of dopant within the one or more CEM traces by replenishing dopant that may be lost during subsequent processing and/or by forming a seal to reduce further loss of dopant from the one or more CEM traces.

Abstract: Subject matter disclosed herein may relate to devices formed from correlated electron material.

Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) device. In embodiments, after formation of the one or more CEM traces, a spacer may be deposited in contact with the one or more CEM traces. The spacer may operate to control an atomic concentration of dopant within the one or more CEM traces by replenishing dopant that may be lost during subsequent processing and/or by forming a seal to reduce further loss of dopant from the one or more CEM traces.

Abstract: Subject matter disclosed herein may relate to devices formed from correlated electron material.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters. In embodiments, CEM devices fabricated at a first stage of a wafer fabrication process, such as a front-end-of-line stage, may differ from CEM devices fabricated at a second stage of a wafer fabrication process, such as a middle-of-line stage or a back-end-of-line stage, for example.

Abstract: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered.

Abstract: Subject matter disclosed herein may relate to devices formed from correlated electron material.

Abstract: An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.

Abstract: A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout data file to further include mask information having at least a first set of trim features associated with one or more redundant metal portions and one or more active metal portions of the layout data file. The method also comprises determining the one or more redundant metal portions to be perforated. The method further comprises modifying the mask information to further include a second set of trim features for perforating the one or more redundant metal portions. The first set of trim features and the second set of trim features are associated with a trim mask of the SAMP process.

Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) device. In embodiments, after formation of the one or more CEM traces, a spacer may be deposited in contact with the one or more CEM traces. The spacer may operate to control an atomic concentration of dopant within the one or more CEM traces by replenishing dopant that may be lost during subsequent processing and/or by forming a seal to reduce further loss of dopant from the one or more CEM traces.

Abstract: Subject matter disclosed herein may relate to devices formed from correlated electron material.

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

Abstract: Various implementations described herein are directed to systems and methods for mitigating contact resistance. In one implementation, a method may include analyzing operating conditions for cells of an integrated circuit. The method may include selectively marking instances of the cells having timing degradation along a critical path of the integrated circuit. The method may include reducing contact resistance for the selectively marked instances of the cells having timing degradation.

Abstract: A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout data file to further include mask information having at least a first set of trim features associated with one or more redundant metal portions and one or more active metal portions of the layout data file. The method also comprises determining the one or more redundant metal portions to be perforated. The method further comprises modifying the mask information to further include a second set of trim features for perforating the one or more redundant metal portions. The first set of trim features and the second set of trim features are associated with a trim mask of the SAMP process.

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.