Patents by Inventor Gregory S. Spencer
Gregory S. Spencer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11383843Abstract: An aircraft tray table retention assembly may include a seat magnetic component installed within a rear bezel of an aircraft seat, and a tray table magnetic component installed within an aircraft tray table. The aircraft tray table may be coupled to the aircraft seat via at least one of one or more hinges or a set of rails, and may be configured to actuate between a stowed position and a deployed position via the at least one of one or more hinges or a set of rails. The tray table magnetic component may be configured to engage the seat magnetic component when the aircraft tray table is in the stowed position. The aircraft tray table retention assembly may include a tray magnetic component configured to engage the tray table magnetic component when the aircraft tray table is in the deployed position.Type: GrantFiled: October 27, 2020Date of Patent: July 12, 2022Assignee: B/E Aerospace, Inc.Inventors: Jackson R Wanner, Gregory S. Spencer, Varun Raman, Hans Huijsing
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Publication number: 20220127003Abstract: An aircraft tray table retention assembly may include a seat magnetic component installed within a rear bezel of an aircraft seat, and a tray table magnetic component installed within an aircraft tray table. The aircraft tray table may be coupled to the aircraft seat via at least one of one or more hinges or a set of rails, and may be configured to actuate between a stowed position and a deployed position via the at least one of one or more hinges or a set of rails. The tray table magnetic component may be configured to engage the seat magnetic component when the aircraft tray table is in the stowed position. The aircraft tray table retention assembly may include a tray magnetic component configured to engage the tray table magnetic component when the aircraft tray table is in the deployed position.Type: ApplicationFiled: October 27, 2020Publication date: April 28, 2022Applicants: Koninklijke Fabriek Inventum B.V., B/E Aerospace, Inc.Inventors: Jackson R Wanner, Gregory S. Spencer, Varun Raman, Hans Huijsing
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Patent number: 10769724Abstract: The system and method allows a vehicle loan organization to generate multiple, customized vehicle loan offers to an applicant for different types of vehicles in an automated fashion. The system and method calculates an acquisition score to better determine the riskiness of offering a vehicle loan to a potential applicant. Additionally, the system and method automates underwriting decisions by automatically approving, denying, or referring vehicle loan applications. For vehicle loan applications that are referred for manual underwriting, the system determines the appropriate credit analyst to use based on the application's complexity, the analyst's expertise, and the analyst's availability. Further, the system uses credit data to calculate a maximum term, amount, and LTV ratio for potential vehicle loans. Also, the system considers the applicant's collateral before approving a vehicle loan. For qualified, approved applicants, the system generates multiple, customized vehicle loan offers for the applicant.Type: GrantFiled: October 25, 2018Date of Patent: September 8, 2020Assignee: STATE FARM MUTUAL AUTOMOBILE INSURANCE COMPANYInventors: Adam T. Shapley, Richard G. Sopek, Jennifer A. Keegan, Gregory S. Spencer, Melinda A. Walker
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Publication number: 20200122622Abstract: An armrest assembly and aircraft passenger seat including the same, the armrest assembly including an arm having a top cutout and a cup holder insert disposed within the top cutout and retained on the arm by front and rear arm caps affixed atop the arm that overlap portions of the installed cup holder insert, the cup holder insert including a recessed center portion at depth within the arm and disposed between upstanding concave end walls, the cup holder insert usable to secure a beverage or other items when the arm is in a deployed use position.Type: ApplicationFiled: October 19, 2018Publication date: April 23, 2020Inventor: Gregory S. Spencer
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Patent number: 10625650Abstract: An armrest assembly and aircraft passenger seat including the same, the armrest assembly including an arm having a top cutout and a cup holder insert disposed within the top cutout and retained on the arm by front and rear arm caps affixed atop the arm that overlap portions of the installed cup holder insert, the cup holder insert including a recessed center portion at depth within the arm and disposed between upstanding concave end walls, the cup holder insert usable to secure a beverage or other items when the arm is in a deployed use position.Type: GrantFiled: October 19, 2018Date of Patent: April 21, 2020Assignee: B/E Aerospace, Inc.Inventor: Gregory S. Spencer
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Patent number: 10163156Abstract: The system and method allows a vehicle loan organization to generate multiple, customized vehicle loan offers to an applicant for different types of vehicles in an automated fashion. The system and method calculates an acquisition score to better determine the riskiness of offering a vehicle loan to a potential applicant. Additionally, the system and method automates underwriting decisions by automatically approving, denying, or referring vehicle loan applications. For vehicle loan applications that are referred for manual underwriting, the system determines the appropriate credit analyst to use based on the application's complexity, the analyst's expertise, and the analyst's availability. Further, the system uses credit data to calculate a maximum term, amount, and LTV ratio for potential vehicle loans. Also, the system considers the applicant's collateral before approving a vehicle loan. For qualified, approved applicants, the system generates multiple, customized vehicle loan offers for the applicant.Type: GrantFiled: September 12, 2014Date of Patent: December 25, 2018Assignee: STATE FARM MUTUAL AUTOMOBILE INSURANCE COMPANYInventors: Adam T. Shapley, Richard G. Sopek, Jennifer A. Keegan, Gregory S. Spencer, Melinda A. Walker
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Patent number: 9209078Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.Type: GrantFiled: March 31, 2014Date of Patent: December 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Gregory S. Spencer, Philip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
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Publication number: 20140213050Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: GREGORY S. SPENCER, Philip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
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Patent number: 8722530Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.Type: GrantFiled: July 28, 2011Date of Patent: May 13, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Gregory S. Spencer, Phillip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
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Publication number: 20130313668Abstract: A photronic device includes a substrate having an opening through the substrate. The photronic device further includes an insulating layer over the substrate including over the opening. The photronic device further includes an active layer over the insulating layer. The photronic device further includes a photoactive device formed in the active layer, wherein the photoactive device is over the opening. The photronic device further includes active electronic circuitry formed in the active layer. The photronic device further includes a reflective layer on the insulating layer in the opening.Type: ApplicationFiled: May 24, 2012Publication date: November 28, 2013Inventors: Gregory S. Spencer, John R. Alvis, Hsiao-Hui Chen, Joseph F. Orcutt, Srivatsa G. Kundalgurki
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Publication number: 20130029485Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Inventors: Gregory S. Spencer, Phillip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
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Patent number: 8242564Abstract: A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.Type: GrantFiled: December 7, 2011Date of Patent: August 14, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Gregory S. Spencer, Jill C. Hildreth, Robert E. Jones
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Publication number: 20120080730Abstract: A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.Type: ApplicationFiled: December 7, 2011Publication date: April 5, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: GREGORY S. SPENCER, Jill C. Hldreth, Robert E. Jones
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Patent number: 8093084Abstract: A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer.Type: GrantFiled: April 30, 2009Date of Patent: January 10, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Gregory S. Spencer, Jill C. Hildreth, Robert E. Jones
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Publication number: 20110223706Abstract: A photodetector is formed to have a germanium detector on a waveguide. The germanium detector has a first surface on the waveguide and a second surface that, when exposed to ambient conditions, forms germanium oxide. In a processing platform, an oxygen-free plasma is applied to the second surface. The oxygen-free plasma removes oxygen that is bonded to germanium at the second surface. A cap layer is formed on the second surface prior to removing the germanium detector from the processing platform.Type: ApplicationFiled: March 10, 2010Publication date: September 15, 2011Inventors: JILL C. HILDRETH, Stanley M. Filipiak, Marc A. Rossow, Gregory S. Spencer, Bret T. Wilkerson
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Patent number: 7911002Abstract: A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.Type: GrantFiled: December 18, 2009Date of Patent: March 22, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Voon-Yew Thean, Marc Rossow, Gregory S. Spencer, Tab A. Stephens, Dina H. Triyoso, Victor H. Vartanian
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Publication number: 20110027950Abstract: A method is provided for integrating a germanium photodetector with a CMOS circuit. The method comprises: forming first and second isolation regions in a silicon substrate; forming a gate electrode in the first isolation region; implanting source/drain extensions in the silicon substrate adjacent to the gate electrode; forming a first sidewall spacer on the gate electrode; implanting source/drain regions in the silicon substrate; removing the first sidewall spacer from the gate electrode; forming a first protective layer over the first and second isolation regions; removing a portion of the first protective layer to form an opening over the second isolation region; forming a semiconductor material comprising germanium in the opening; forming a second protective layer over the first and second isolation regions; selectively removing the first and second protective layers from the first isolation region; and forming contacts to the transistor and to the semiconductor material.Type: ApplicationFiled: July 28, 2009Publication date: February 3, 2011Inventors: Robert E. Jones, Dean J. Denning, Gregory S. Spencer
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Patent number: 7871854Abstract: A method includes forming a first opening in a top surface of a semiconductor substrate, performing an implant into the top surface to form a doped region, epitaxially growing a semiconductor layer in the first opening along a bottom of the first opening and along sidewalls of the first opening, wherein the epitaxially growing comprises in-situ doping the semiconductor layer, filling the first opening with a dielectric material, forming a second opening in the dielectric material, wherein a bottom of the second opening exposes the epitaxially grown semiconductor layer and sidewalls of the second opening expose the dielectric material; and filling the second opening with a semiconductor material, wherein the semiconductor material comprises a top electrode and a bottom electrode. The bottom electrode is in electrical contact with the semiconductor layer which is in electrical contact with the doped region. The doped region is laterally adjacent the semiconductor material.Type: GrantFiled: August 19, 2009Date of Patent: January 18, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Gregory S. Spencer, Robert E. Jones
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Patent number: 7846803Abstract: A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time.Type: GrantFiled: May 31, 2007Date of Patent: December 7, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Gregory S. Spencer, Vishal P. Trivedi
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Publication number: 20100276735Abstract: A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer.Type: ApplicationFiled: April 30, 2009Publication date: November 4, 2010Inventors: Gregory S. Spencer, Jill C. Hildreth, Robert E. Jones