Patents by Inventor Gregory Starr
Gregory Starr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9490812Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: January 28, 2014Date of Patent: November 8, 2016Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 8680913Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: May 13, 2013Date of Patent: March 25, 2014Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 8441314Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: July 26, 2012Date of Patent: May 14, 2013Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 8364738Abstract: In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.Type: GrantFiled: March 2, 2010Date of Patent: January 29, 2013Assignee: Altera CorporationInventors: Martin Langhammer, Leon Zheng, Chiao Kai Hwang, Gregory Starr
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Patent number: 8253484Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: October 28, 2011Date of Patent: August 28, 2012Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 8072260Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: November 22, 2010Date of Patent: December 6, 2011Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 7859329Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: November 25, 2009Date of Patent: December 28, 2010Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 7698358Abstract: In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.Type: GrantFiled: December 24, 2003Date of Patent: April 13, 2010Assignee: Altera CorporationInventors: Martin Langhammer, Leon Zheng, Chiao Kai Hwang, Gregory Starr
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Patent number: 7646237Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: July 30, 2007Date of Patent: January 12, 2010Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y Chang
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Patent number: 7623609Abstract: Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The circuitry selects two phase-adjacent ones of the candidate clock signals that are currently the two best candidates for final selection. The circuitry makes a final selection of the generally better one of these two best candidates in a way that avoids unproductive switching back and forth between these two best candidates.Type: GrantFiled: October 10, 2008Date of Patent: November 24, 2009Assignee: Altera CorporationInventors: Richard Yen-Hsiang Chang, Gregory Starr
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Publication number: 20090041170Abstract: Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The circuitry selects two phase-adjacent ones of the candidate clock signals that are currently the two best candidates for final selection. The circuitry makes a final selection of the generally better one of these two best candidates in a way that avoids unproductive switching back and forth between these two best candidates.Type: ApplicationFiled: October 10, 2008Publication date: February 12, 2009Inventors: Richard Yen-Hsiang Chang, Gregory Starr
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Patent number: 7453968Abstract: Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The circuitry selects two phase-adjacent ones of the candidate clock signals that are currently the two best candidates for final selection. The circuitry makes a final selection of the generally better one of these two best candidates in a way that avoids unproductive switching back and forth between these two best candidates.Type: GrantFiled: May 18, 2004Date of Patent: November 18, 2008Assignee: Altera CorporationInventors: Richard Yen-Hsiang Chang, Gregory Starr
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Patent number: 7437401Abstract: A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.Type: GrantFiled: February 20, 2004Date of Patent: October 14, 2008Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Gregory Starr, William Hwang, Kumara Tharmalingam
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Patent number: 7346644Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one or more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.Type: GrantFiled: August 17, 2006Date of Patent: March 18, 2008Assignee: Altera CorporationInventors: Martin Langhammer, Gregory Starr, Chiao Kai Hwang
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Patent number: 7307459Abstract: A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections are provided between those components and the remainder of the PLD so that if the PLL is not being used in a particular user design of the PLD, the PLL modular components may be used by other portions of the PLD. Similarly, those connections allow other portions of the PLD to be used in place of one or more of the modular components where more complex or special filtering than can be provided by the modular components is required.Type: GrantFiled: March 16, 2006Date of Patent: December 11, 2007Assignee: Altera CorporationInventor: Gregory Starr
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Patent number: 7286007Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: November 17, 2005Date of Patent: October 23, 2007Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y Chang
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Patent number: 7216139Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.Type: GrantFiled: December 28, 2005Date of Patent: May 8, 2007Assignee: Altera CorporationInventors: Martin Langhammer, Chiao Kai Hwang, Gregory Starr
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Patent number: 7193443Abstract: Various embodiments for differential output circuits with reduced transistor sizes and reduced DC currents provide efficient and flexible differential driver circuits. AC current boosting enables the switching transistors that drive the output nodes to be smaller in size. The AC current boost circuitry is shared by both switching current paths in the differential output circuit to reduce size and parasitic effects. Similarly, DC current circuitry is also shared by both switching current paths. The AC boost circuit and the DC bias circuit are made programmable to enable the output circuit to support multiple I/O standards with different specifications.Type: GrantFiled: May 23, 2005Date of Patent: March 20, 2007Assignee: Altera CorporationInventors: Mian Z. Smith, Gregory Starr
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Patent number: 7180334Abstract: Method and apparatus for locking a phase lock loop, where the method includes selecting a frequency window corresponding to a VCO output frequency, selecting a control voltage corresponding to the frequency window and providing the control voltage to the control voltage circuit which subsequently uses the selected control voltage as the starting control voltage of the phase lock loop.Type: GrantFiled: April 3, 2003Date of Patent: February 20, 2007Assignee: Altera CorporationInventor: Gregory Starr
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Patent number: 7142010Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.Type: GrantFiled: December 19, 2003Date of Patent: November 28, 2006Assignee: Altera CorporationInventors: Martin Langhammer, Chiao Kai Hwang, Gregory Starr