Abstract: A cover sheet applicator for applying a cover sheet from a roll, for example, paper or plastic, to a sheet of material, for example, glass or screen printed adhesives. The applicator comprises a frame and a first conveyor for receiving a sheet of material to be covered. Cover material is drawn from the roll by drive rollers. A cutting mechanism cuts the cover material to a predetermined length to form the cover sheet. The cover sheet is received and retained on a vacuum conveyor which is inclined with respect to the first conveyor, for example, an endless belt. A control is provided to sequence the operation of the first conveyor, the cutting mechanism and the vacuum conveyor. When the lead edge of the cover sheet and the sheet of material are aligned, the vacuum is released and upon further advance of the sheet of material, the cover sheet is applied to the top of the sheet of material.

Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Abstract: A method of automatic in-line forming of a material stack comprising the steps of feeding a base in sheet form or from a roll to a predetermined position, simultaneously feeding a first layer from a first roll for placement on one side of the base in sheet form and a second layer from a second roll for placement on the opposite side of the base in sheet form. The base, the first layer from the first roll, and the second layer from the second roll are moved together to a cutting station and are advanced a predetermined length. The first layer and the second layer are cut together to the predetermined length to form the desired stack, with the base between the first and second layers. In another aspect, the invention comprises apparatus for automatic in-line forming of a material stack comprising a main frame, a conveyor on the main frame for feeding a base material. A first layer of material is fed from a first roll onto one surface of the base material.

Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Abstract: A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.

Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Abstract: A cutting machine for cutting long lengths of sheet material, roll material, or web material into predetermined or discrete lengths comprises a frame having a stationary blade extending transversely of the frame and a carriage movable transversely of the material to be cut having a movable blade thereon that cooperates with the stationary blade to cut material. The movable blade is mounted on the carriage so that it can be canted at an angle with respect to the stationary blade during transverse movement of the carriage in one direction and can be oppositely canted at an angle with respect to the stationary blade during movement of the carriage in the opposite direction. In one embodiment, a toggle mechanism is used to cant the movable blade. In a second embodiment, a fluid cylinder is used to cant the movable blade.

Abstract: A cutting machine for sheet material comprising a frame, a stationary knife on the frame and a reciprocating blade cooperating with the stationary knife. A motor on the frame is connected to a gear reducer that is in turn connected to a single push rod through a crank. The push rod is operatively connected to a torque tube that is connected adjacent its ends by link means to the reciprocating blade. Rotation of the crank by the gear reducer will actuate the single push rod and the torque tube operatively connected thereto to reciprocate the reciprocating blade. Spring means for assisting movement of the reciprocating blade are readily adjusted from exterior of the frame of the cutting machine. A rotatable cam follower on the reciprocating blade engages a guide block on the frame for moving the reciprocating blade into proper cooperative engagement with the stationary knife in use.

Abstract: A machine for feeding and cutting sheet material includes a housing and a framework pivoted on the housing to permit loading of sheet material into the machine. A feed roll is journalled in the housing. A cooperating pressure roll is journalled on the framework. A spring is adjustably carried on the framework for adjusting the pressure of the pressure roll toward the feed roll. A knife blade on the framework, and fixed to the framework cooperates with a movable knife blade in the housing for cutting predetermined lengths of sheet material. A cam follower bearing is provided in the housing to help guide movement of the knife blade in the housing. A spring adjustment is provided in the linkage connecting the cylinder driving the movable knife blade and the movable knife blade for varying the force of the movable knife blade against the cam roller bearing.