Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

Abstract: A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.

Abstract: Embodiments include load-balancing a plurality of simultaneous threads of a processor. An example method includes computing a minimum group count for a thread from the plurality of threads. The minimum group count indicates a minimum number of groups of instructions to be assigned to the thread. The method further includes computing a maximum allowed group count for the thread. The maximum allowed group count indicates a maximum number of groups of instructions to be assigned to the thread. The method further includes issuing one or more groups of instructions for execution by the thread based on the minimum group count and the maximum allowed group count for the thread.

Abstract: Managing a global completion table used to track progress of groups of instructions, in which each group of instructions includes one or more instructions. Entries of the global completion table are allocated to the groups of instructions from a freelist of entries. That is, entries are allocated from a pool of entries, rather than allocating entries in-order in a circular queue.

Abstract: Managing a global completion table used to track progress of groups of instructions, in which each group of instructions includes one or more instructions. Entries of the global completion table are allocated to the groups of instructions from a freelist of entries. That is, entries are allocated from a pool of entries, rather than allocating entries in-order in a circular queue.

Abstract: Dynamic resource allocation is provided in which additional resources, such as additional architected registers, are provided to an instruction, if it is determined that resources in addition to those configured to be provided to the instruction are to be used for the particular instruction. An instruction to be executed is dispatched on a pipe of a pipeline and that pipe is configured to have a set number of architected registers for use by the instruction. However, if one or more other architected registers are needed, those additional architected registers are dynamically allocated to the instruction by assigning one or more source ports of an additional pipe to the instruction.

Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises detecting memory address information corresponding to accessed data in a first instruction, and detecting memory address information corresponding to accessed data in a second instruction. The method further comprises comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. In addition the method comprise executing the second instruction using the accessed data from the first instruction and detecting an error from the execution of the second instruction.

Abstract: Techniques for generating a design structure for cache power reduction are described herein. In one example, a system includes logic to detect memory address information corresponding to accessed data in a first instruction, and detect memory address information corresponding to accessed data in a second instruction. The logic can also compare the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detect, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. The logic can also execute the second instruction using the accessed data from the first instruction.

Abstract: An apparatus for processing instructions includes a mapping unit comprising a plurality of mappers wherein each mapper of the plurality of mappers maps a logical sub-register reference to a physical sub-register reference, a decoding unit configured to receive an instruction and determine a plurality of logical sub-register references therefrom, and an execution unit. The mapping unit may be configured to distribute the plurality of logical sub-register references amongst the plurality of mappers according to at least one bit in the instruction and provide a corresponding plurality of physical sub-register references. The execution unit may be configured to execute the instruction using the plurality of physical sub-register references. Corresponding methods are also disclosed herein.

Abstract: Embodiments include method, systems and computer program products for searching a social network for media content. Aspects include identifying one or more available resources for execution by the processor, determining a maximum number of resources the processor can utilize in executing an instruction group, and grouping the one or more available resources into one or more resource groups, wherein each of the one or more resource groups has a size equal to the maximum number. Aspects also include receiving a request from a decode logic for a number of resources for execution and dispatching one of the one or more resource groups in response to the request by providing the number of resources for execution to the processor and sending remaining resources in the one of the one or more resource groups to a recycle queue.

Abstract: Embodiments include method, systems and computer program products for searching a social network for media content. Aspects include identifying one or more available resources for execution by the processor, determining a maximum number of resources the processor can utilize in executing an instruction group, and grouping the one or more available resources into one or more resource groups, wherein each of the one or more resource groups has a size equal to the maximum number. Aspects also include receiving a request from a decode logic for a number of resources for execution and dispatching one of the one or more resource groups in response to the request by providing the number of resources for execution to the processor and sending remaining resources in the one of the one or more resource groups to a recycle queue.

Abstract: Embodiments include method, systems and computer program products for searching a social network for media content. Aspects include identifying one or more available resources for execution by the processor, determining a maximum number of resources the processor can utilize in executing an instruction group, and grouping the one or more available resources into one or more resource groups, wherein each of the one or more resource groups has a size equal to the maximum number. Aspects also include receiving a request from a decode logic for a number of resources for execution and dispatching one of the one or more resource groups in response to the request by providing the number of resources for execution to the processor and sending remaining resources in the one of the one or more resource groups to a recycle queue.

Abstract: Embodiments include method, systems and computer program products for searching a social network for media content. Aspects include identifying one or more available resources for execution by the processor, determining a maximum number of resources the processor can utilize in executing an instruction group, and grouping the one or more available resources into one or more resource groups, wherein each of the one or more resource groups has a size equal to the maximum number. Aspects also include receiving a request from a decode logic for a number of resources for execution and dispatching one of the one or more resource groups in response to the request by providing the number of resources for execution to the processor and sending remaining resources in the one of the one or more resource groups to a recycle queue.

Abstract: Embodiments include method, systems and computer program products for searching a social network for media content. Aspects include identifying one or more available resources for execution by the processor, determining a maximum number of resources the processor can utilize in executing an instruction group, and grouping the one or more available resources into one or more resource groups, wherein each of the one or more resource groups has a size equal to the maximum number. Aspects also include receiving a request from a decode logic for a number of resources for execution and dispatching one of the one or more resource groups in response to the request by providing the number of resources for execution to the processor and sending remaining resources in the one of the one or more resource groups to a recycle queue.

Abstract: An apparatus for processing instructions includes a mapping unit comprising a plurality of mappers wherein each mapper of the plurality of mappers maps a logical sub-register reference to a physical sub-register reference, a decoding unit configured to receive an instruction and determine a plurality of logical sub-register references therefrom, and an execution unit. The mapping unit may be configured to distribute the plurality of logical sub-register references amongst the plurality of mappers according to at least one bit in the instruction and provide a corresponding plurality of physical sub-register references. The execution unit may be configured to execute the instruction using the plurality of physical sub-register references. Corresponding methods are also disclosed herein.

Abstract: A system provides complex branch execution hardware and a hardware-based Multiplexer (MUX) to multiplex a fetch address of a future branch and a preloaded branch fetch address to create an index hash value that is used to index a branch target prediction table for execution by a processor core, in order to reduce branch mis-prediction by preloading.

Abstract: A method and information processing system manage load and store operations that can be executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag, the load instruction becomes dependent upon all store instructions associated with a substantially similar hazard indicating flag.

Abstract: Dynamic resource allocation is provided in which additional resources, such as additional architected registers, are provided to an instruction, if it is determined that resources in addition to those configured to be provided to the instruction are to be used for the particular instruction. An instruction to be executed is dispatched on a pipe of a pipeline and that pipe is configured to have a set number of architected registers for use by the instruction. However, if one or more other architected registers are needed, those additional architected registers are dynamically allocated to the instruction by assigning one or more source ports of an additional pipe to the instruction.

Abstract: Techniques for generating a design structure for cache power reduction are described herein. In one example, a system includes logic to detect memory address information corresponding to accessed data in a first instruction, and detect memory address information corresponding to accessed data in a second instruction. The logic can also compare the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detect, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. The logic can also execute the second instruction using the accessed data from the first instruction.