Abstract: Illustrative embodiments provide a method for improved link stack misprediction resolution using a rename structure for tracking the link stack processing, in order to quickly resolve link stack corruption from mispredicted function returns. The method comprises establishing a set of physical data structures forming a common pool and an operation control table. Maintaining, within the common pool, a plurality of entries for a plurality of speculative instructions and a plurality of non-speculative instructions. And determining one speculative instruction to be a bad prediction speculative entry, identifying related entries to form a collection, and discarding the collection.

Abstract: A system for co-generation of electricity combining a hydrocarbon catalytic reformer, an SOFC assembly and a generator driven by a gas turbine. The fuel cell assembly recycles a high percentage of anode exhaust gas into the reformer. Oxygen for reforming is derived from water in an endothermic process. The stack exit temperature is normally above 800° C. DC power from the fuel cell assembly and AC power from the gas turbine generator are directed to a power conditioner. Anode exhaust gas including carbon monoxide and hydrogen is divided into a plurality of portions by which heat may be added to the reforming, gas turbine, and cathode air heating processes. Water may be recovered from the exhaust. A power system in accordance with the invention is capable of operating at a higher total efficiency than either the fuel cell component or the gas turbine component alone.

Abstract: A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on an address retrieved from a program counter. The first hashed address may be used to index into the instruction cache. The second hashed address may be used to index into the prefetch buffer. If the value stored in the indexed entry in an effective address array of the instruction cache does not equal the value of the third hash of the address (an instruction cache miss), then the instructions in the indexed entry in the prefetch buffer are selected. In this manner, instructions may be selected in the prefetch buffer in the event of a miss in the instruction cache with a zero cycle penalty.

Abstract: A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on an address retrieved from a program counter. The first hashed address may be used to index into the instruction cache. The second hashed address may be used to index into the prefetch buffer. If the value stored in the indexed entry in an effective address array of the instruction cache does not equal the value of the third hash of the address (an instruction cache miss), then the instructions in the indexed entry in the prefetch buffer are selected. In this manner, instructions may be selected in the prefetch buffer in the event of a miss in the instruction cache with a zero cycle penalty.