Abstract: A radar system includes a signal generator configured to generate an RF signal; a modulator configured to generate an RF test signal by modulating the RF signal with a test signal; a transmitting channel configured to generate an RF output signal based on the RF signal; and a receiving channel configured to receive an antenna signal and the RF test signal and down-convert a superposition of the two signals to baseband by means of a mixer in order to obtain a baseband signal. The radar system further includes an analog-to-digital converter configured to generate a digital radar signal based on the baseband signal, and a computing unit configured to filter the digital radar signal by means of a digital filter, wherein the filter characteristic of the digital filter has a pass band, a transition band, and a stop band. The test signal has a frequency in the transition band.

Abstract: A device may include a test signal generator and a receive antenna input. The device may include a switchable impedance matching circuit, coupled to the test signal generator and to a receive chain, to cause an impedance matching between the test signal generator and a component of the receive chain to be increased during a monitoring phase. The impedance matching during the monitoring phase enables one or more measurements based on a test signal generated by the test signal generator. The switchable impedance matching circuit may cause a partial impedance mismatching between the test signal generator and the component of the receive chain during a verification phase associated with verifying a return of the switchable impedance matching circuit to an impedance matching caused during the operational phase. The device may include a control circuit to verify operation of the returning of the switchable impedance matching circuit in the verification phase.

Abstract: A radar semiconductor chip includes a radar circuit component configured to generate at least part of a frequency-modulated ramp signal or process at least part of a reflected frequency-modulated ramp signal according to a control parameter; a memory configured to store a sequencing program associated with regulating the control parameter, wherein the sequencing program specifies a first data source, external to the sequencing program, that is configured to provide a first data value corresponding to the control parameter; and a decoder configured to read the sequencing program, access the first data value from the first data source specified by the sequencing program, derive a first control value for the control parameter from the first data value, and provide the first control value to the radar circuit component. The radar circuit component regulates a controlled circuit function in accordance with the control parameter based on the first control value.

Abstract: A device may include a receive antenna input to couple a receive chain of the device to a receive antenna. The device may include a test signal generator. The device may include a switchable impedance matching circuit coupled to the test signal generator and to the receive chain to cause an impedance matching between the test signal generator and at least one component of the receive chain to depend on an impedance of the receive antenna in an antenna monitoring phase. The antenna monitoring phase may be associated with determining an impedance mismatching of the receive antenna. The device may include a control circuit to determine the impedance mismatching of the receive antenna in the antenna monitoring phase.

Abstract: The present disclosure relates to a radar apparatus including a transmitter for transmitting a frequency-modulated continuous-wave radar signal, wherein the transmitter is configured to generate the continuous-wave radar signal with a sinusoidally varying modulation frequency, a receiver for receiving a reflection signal of the frequency-modulated continuous-wave radar signal, which is reflected by at least one object, and for mixing the reflection signal with the frequency-modulated continuous-wave radar signal in order to obtain a downmixed reception signal, and a device for correlating the downmixed reception signal with at least one pattern signal which is based on the modulation frequency and a predetermined distance.

Abstract: A method for calibrating a radar system includes generating an RF oscillator signal and distributing the RF oscillator signal to a plurality of phase shifters each providing a respective phase-shifted RF oscillator signal; receiving the phase-shifted RF oscillator signals by corresponding radar chips and radiating the phase-shifted RF oscillator signal via a first RF output channel of a first one of the radar chips; receiving a back-scattered signal by at least one RF input channel of each radar chip and generating a plurality of base-band signals by down-converting the received signals into a base band using the phase-shifted RF oscillator signals received by the corresponding radar chips; determining a phase for each base-band signal; and adjusting the phase shifts caused by the phase shifters such that the phases of the base-band signals match a predefined phase-over-antenna-position characteristic.

Abstract: A radar system is provided. The radar system includes a first radar chip, a second radar chip and a third radar chip. Further, the second radar chip includes a first coupling circuit. Additionally, the third radar chip includes a second coupling circuit. A control circuit is configured to control the first coupling circuit and the second coupling circuit. The first radar chip includes an analysis circuit configured to determine information indicating a reflected wave component. The analysis circuit is further configured to determine, based on the determined information, whether distributions of the oscillation signal to the first and second input nodes via the first and second signal lines are equal.

Abstract: A radio frequency circuit includes an input terminal configured to receive a reception signal from an antenna; a reception signal path coupled to the input terminal and including a mixer and an analog-to-digital converter (ADC), where the ADC generates a digital signal representing an input signal to the ADC; a test signal generator configured to generate a test signal that is injected into the reception signal path while the reception signal propagates along the reception signal path; a digital signal processor configured to receive the digital signal from a digital portion of the reception signal path, and analyze a frequency response of the digital signal; and a subtractor coupled to the digital portion of the reception signal path, the subtractor configured to remove test frequency components resulting from an injection of the test signal into the reception signal path from the digital signal.

Abstract: A device may include a test signal generator and a receive antenna input. The device may include a switchable impedance matching circuit, coupled to the test signal generator and to a receive chain, to cause an impedance matching between the test signal generator and a component of the receive chain to be increased during a monitoring phase. The impedance matching during the monitoring phase enables one or more measurements based on a test signal generated by the test signal generator. The switchable impedance matching circuit may cause a partial impedance mismatching between the test signal generator and the component of the receive chain during a verification phase associated with verifying a return of the switchable impedance matching circuit to an impedance matching caused during the operational phase. The device may include a control circuit to verify operation of the returning of the switchable impedance matching circuit in the verification phase.

Abstract: An integrated circuit includes a first input port configured to receive a supply voltage from a switched-mode power supply (SMPS), where frequency components of the supply voltage include harmonics of a reference frequency, where the reference frequency is equal to a first frequency divided by a factor; and a spurious components cancellation circuit coupled to the first input port, where the spurious components cancellation circuit is configured to: generate a first clock signal having the reference frequency; adjust an amplitude and a phase of the first clock signal to form a compensation signal; and add the compensation signal to the supply voltage to produce a modified supply voltage with reduced frequency components at one or more harmonic frequencies of the reference frequency.

Abstract: A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.

Abstract: A device may include a test signal generator and a receive antenna input. The device may include a switchable impedance matching circuit, coupled to the test signal generator and to a receive chain, to cause an impedance matching between the test signal generator and a component of the receive chain to be increased during a monitoring phase. The impedance matching during the monitoring phase enables one or more measurements based on a test signal generated by the test signal generator. The switchable impedance matching circuit may cause a partial impedance mismatching between the test signal generator and the component of the receive chain during a verification phase associated with verifying a return of the switchable impedance matching circuit to an impedance matching caused during the operational phase. The device may include a control circuit to verify operation of the returning of the switchable impedance matching circuit in the verification phase.

Abstract: A radar system includes a signal generator configured to generate an RF signal; a modulator configured to generate an RF test signal by modulating the RF signal with a test signal; a transmitting channel configured to generate an RF output signal based on the RF signal; and a receiving channel configured to receive an antenna signal and the RF test signal and down-convert a superposition of the two signals to baseband by means of a mixer in order to obtain a baseband signal. The radar system further includes an analog-to-digital converter configured to generate a digital radar signal based on the baseband signal, and a computing unit configured to filter the digital radar signal by means of a digital filter, wherein the filter characteristic of the digital filter has a pass band, a transition band, and a stop band. The test signal has a frequency in the transition band.

Abstract: A method for use in a radar device is described herein. In accordance some implementations, the method includes generating an RF oscillator signal which includes frequency-modulated chirps, amplitude-modulating the RF oscillator signal by a modulation signal, and transmitting the amplitude-modulated RF oscillator signal via at least one antenna. In some implementations, the method may further include receiving an RF signal that includes frequency-modulated chirp echo signals from a target object, down-converting the received RF signal into a base band using the RF oscillator signal for providing a base band signal, and processing the base band signal to detect information included in the modulation signal.

Abstract: A radar system is provided. The radar system includes a first radar chip, a second radar chip and a third radar chip. Further, the second radar chip includes a first coupling circuit. Additionally, the third radar chip includes a second coupling circuit. A control circuit is configured to control the first coupling circuit and the second coupling circuit. The first radar chip includes an analysis circuit configured to determine information indicating a reflected wave component. The analysis circuit is further configured to determine, based on the determined information, whether distributions of the oscillation signal to the first and second input nodes via the first and second signal lines are equal.

Abstract: A radio frequency circuit includes an input terminal configured to receive a reception signal from an antenna; a reception signal path coupled to the input terminal and including a mixer and an analog-to-digital converter (ADC), where the ADC generates a digital signal representing an input signal to the ADC; a test signal generator configured to generate a test signal that is injected into the reception signal path while the reception signal propagates along the reception signal path; a digital signal processor configured to receive the digital signal from a digital portion of the reception signal path, and analyze a frequency response of the digital signal; and a subtractor coupled to the digital portion of the reception signal path, the subtractor configured to remove test frequency components resulting from an injection of the test signal into the reception signal path from the digital signal.

Abstract: A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.

Abstract: A phase-locked loop (PLL) for a radar system includes an oscillator configured to have an output frequency and a multi-modulus divider (MMD) configured to implement successive frequency modulation ramps of the oscillator output frequency, each frequency modulation ramp beginning at a first frequency and ending at a second frequency. The PLL is operated by downmixing an output of the MMD to a frequency above zero Hertz, measuring the downmixed output of the MMD to generate a plurality of MMD output measurements for each frequency modulation ramp, and calculating the frequency of the MMD based on the plurality of MMD output measurements for each frequency modulation ramp.

Abstract: An apparatus for adjusting a component in a receiver system to eliminate distortion. The apparatus may include a receiver system and a tuning circuit. The receiver system may process a tracking signal to generate an output signal. The tracking signal may include a radio frequency (RF) signal and a test signal. The processing of the first tracking signal may introduce a distortion into the output signal. The tuning circuit may be operatively coupled to the receiver system. The tuning circuit may determine an adjustment value and send the adjustment value to the receiver system. The receiver system may adjust a component of the receiver system using the adjustment value to eliminate the distortion in a second RF signal that is caused by the component.

Abstract: Examples provide a control circuit and a control apparatus, a radio frequency circuit and a radio frequency apparatus, a transceiver, a mobile terminal, methods and computer programs for determining calibration values for a radio frequency circuit. A control circuit (10) is configured to determine calibration values for a radio frequency circuit (100) with a transmit unit (102) coupled to an antenna (104) through an antenna tuner (106). The control circuit (10) is configured to determine the calibration values for the radio frequency circuit (100) based on at least two impedance measurements and based on at least two antenna tuner configurations.