Abstract: An image sensor device and methods thereof. In an example method, a protective layer may be formed over at least one microlens. An adhesive layer may be formed over the protective layer. The adhesive layer may be removed so as to expose the protective layer. The protective layer may be removed so as to expose the at least one microlens, the exposed at least one microlens not including residue from the adhesive layer. The at least one microlens may have an improved functionality due at least in part to the lack of residue from the adhesive layer. In an example, the at least one microlens may be included in an image sensor module.

Abstract: An electronic module comprises a monolithic microelectronic substrate including at least one integrated circuit die, e.g., a plurality of unseparated memory dice or a mixture of different types of integrated circuit dice. The monolithic substrate further includes a redistribution structure disposed on the at least one integrated circuit die and providing a connector contact coupled to the at least one integrated circuit die. For example, the connector contact may be configured as edge connector contact for the module. The redistribution structure may be configured to provide a passive electronic device, e.g., an inductor, capacitor and/or resistor, electrically coupled to the at least one integrated circuit die and/or the redistribution structure may comprise at least one conductive layer configured to provide electrical connection to a contact pad of an electronic device mounted on the substrate. Methods of fabricating electronic modules are also discussed.

Abstract: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Abstract: A solder bump structure may be formed using a dual exposure technique of a photoresist, which may be a positive photoresist. The positive photoresist may be coated on an IC chip. First openings may be formed at first exposed regions of the photoresist by a first exposure process. Metal projections may be formed in the first openings. A second opening may be formed at a second exposed region of the photoresist by a second exposure process. The second exposed region may include non-exposed regions defined by the first exposure process. A solder material may fill the second opening and may be reflowed to form a solder bump. The metal projections may be embedded within the solder bump.

Abstract: An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in a central region of the active surface and an intermediate region between the peripheral and central regions. A protective plate may be attached to the intermediate region of the active surface of the image sensor chip using an adhesive pattern that is sized and configured to maintain a separation distance between the protective plate and the microlens formed on the image sensor chip. Conductive plugs, formed before, during or after the manufacture of the image sensor chip circuitry may provide electrical connection between the chip pads and external connectors.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other.

Abstract: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Abstract: A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

Abstract: An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in a central region of the active surface and an intermediate region between the peripheral and central regions. A protective plate may be attached to the intermediate region of the active surface of the image sensor chip using an adhesive pattern that is sized and configured to maintain a separation distance between the protective plate and the microlens formed on the image sensor chip. Conductive plugs, formed before, during or after the manufacture of the image sensor chip circuitry may provide electrical connection between the chip pads and external connectors.

Abstract: A center pad type integrated circuit chip and a method of forming the same is presented. The chip comprises an integrated circuit chip having chip pads formed on a center region thereof and a jumper. The jumper includes a buffer layer arranged adjacent to a side of the chip pads and a plurality of jump metal lines formed on the buffer layer. The jump metal lines are spaced apart from each other.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other.

Abstract: A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.

Abstract: A center pad type integrated circuit chip and a method of forming the same is presented. The chip comprises an integrated circuit chip having chip pads formed on a center region thereof and a jumper. The jumper includes a buffer layer arranged adjacent to a side of the chip pads and a plurality of jump metal lines formed on the buffer layer. The jump metal lines are spaced apart from each other.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other.

Abstract: A structure for improving electrical performance and interconnection reliability of an integrated circuit in a Wafer Level Packaging (WLP) application comprises an air pad located under an interconnection metal solder pad. Using a low dielectric material such as air underlying the interconnection pad, pad capacitance is reduce, thereby improving the speed of associated electrical signal transitions. By configuring the structure to have interconnection pad supports at only a limited number of pad periphery points, a cured soldered connection can absorb mechanical stresses associated with divergent movement between a connecting wire and the interconnection pad. Such a structure can be manufactured using the steps of: 1) depositing a soluble base material in a cavity on an IC substrate, 2) depositing a metal pad layer on the soluble base layer, and 3) dissolving the soluble base layer, leaving an air gap under the metal pad layer which is supported by the periphery supports.

Abstract: A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.

Abstract: An image sensor device and methods thereof. In an example method, a protective layer may be formed over at least one microlens. An adhesive layer may be formed over the protective layer. The adhesive layer may be removed so as to expose the protective layer. The protective layer may be removed so as to expose the at least one microlens, the exposed at least one microlens not including residue from the adhesive layer. The at least one microlens may have an improved functionality due at least in part to the lack of residue from the adhesive layer. In an example, the at least one microlens may be included in an image sensor module.

Abstract: Example embodiments of the present invention relate to a method of manufacturing an optical device having a transparent cover and a method of manufacturing an optical device module using the optical device. According to an example method of manufacturing the optical device, a semiconductor substrate having a plurality of dies including an effective pixel and a plurality of bonding pads arranged around the effective pixel is prepared. A protective layer may be formed on the semiconductor substrate to selectively cover the effective pixel. An adhesive pattern may be formed to enclose an edge of the effective pixel, and a transparent cover may be attached to correspond to the effective pixel using the adhesive pattern.

Abstract: A method for fabricating a chip-embedded interposer may comprise forming at least one cavity on a silicon substrate, forming a plurality of through vias penetrating the silicon substrate, providing an integrated circuit chip having a plurality of I/O pads, and forming rerouting conductors connected to the I/O pads and the through vias. A stack structure having different kinds of chips may be incorporated at wafer level using the described interposer.

Abstract: A structure for improving electrical performance and interconnection reliability of an integrated circuit in a Wafer Level Packaging (WLP) application comprises an air pad located under an interconnection metal solder pad. Using a low dielectric material such as air underlying the interconnection pad, pad capacitance is reduced, thereby improving the speed of associated electrical signal transitions. By configuring the structure to have interconnection pad supports at only a limited number of pad periphery points, a cured soldered connection can absorb mechanical stresses associated with divergent movement between a connecting wire and the interconnection pad. Such a structure can be manufactured using the steps of: 1) depositing a soluble base material in a cavity on an IC substrate, 2) depositing a metal pad layer on the soluble base layer, and 3) dissolving the soluble base layer, leaving an air gap under the metal pad layer which is supported by the periphery supports.