Abstract: An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1st level and an auxiliary level respectively according to the 1st threshold-voltage distribution curve and a threshold-voltage auxiliary curve when the first and the second storage positions are programmed to the 1st and Nth levels; and programming the first and the second storage positions to the ith level according to the ith threshold-voltage distribution curve when the first and the second storage positions are not to be programmed to the 1st and Nth levels, wherein i is an integer and 1?i?N.

Abstract: A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.

Abstract: The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The first doped regions between the neighbouring trenches are separated from each other. The second doped regions are configured in the substrate under bottoms of the trenches, respectively. The second doped regions and the first doped regions are separated from each other, such that each memory cell includes six physical bits.

Abstract: The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.

Abstract: A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion.

Abstract: An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1st level and an auxiliary level respectively according to the 1st threshold-voltage distribution curve and a threshold-voltage auxiliary curve when the first and the second storage positions are programmed to the 1st and Nth levels; and programming the first and the second storage positions to the ith level according to the ith threshold-voltage distribution curve when the first and the second storage positions are not to be programmed to the 1st and Nth levels, wherein i is an integer and 1?i?N.

Abstract: A micro reactor having micro flow-guiding blocks includes a first gas flow channel, a second gas flow channel and a catalytic converter. There are several flow-guiding portions disposed on the first gas flow channel. Each flow-guiding portion has micro flow-guiding blocks, flow-impact recesses, and catalytic portions. The function of the micro flow-guiding block is to guide a flowing direction of the flow toward the catalytic portion on the flow-impact recess in order to increase a possibility of contacting and chemical reaction with the catalytic portion. So, guiding the flow direction toward the catalytic portion can increase the overall reaction efficiency. More turbulence is generated to obtain a better mixing. Plus, its structure is simple.

Abstract: The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The first doped regions between the neighbouring trenches are separated from each other. The second doped regions are configured in the substrate under bottoms of the trenches, respectively. The second doped regions and the first doped regions are separated from each other, such that each memory cell includes six physical bits.

Abstract: The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.

Abstract: A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.

Abstract: A method for operating a nitride-based flash memory is provided. The operation method includes pre-performing an interference reduction operation (IRO) before the routine programming operating step. Through bias arrangement of the target memory cell, charges are injected into the charge trapping layer mainly above the junction regions of the memory cell before programming so as to reset the influences caused by coupling interference issues. The operation method of this present invention not only reduces coupling interference but also afford a wider operation window.

Abstract: A manufacturing method of fuel cell having micro sensors and polymer layers is disclosed. It include the following steps of: (1) depositing first polymer layer step, (2) first lithographic processing step, (3) depositing chromium layer step, (4) depositing gold layer step, (5) removing first photo-resist layer step, (6) depositing second polymer layer step, (7) second lithographic processing step, (8) plasma etching step, (9) removing second photo-resist layer step, and (10) complete step. About this invention, the polymer layers can protect the micro sensors. The micro sensors can be installed at a specific location in the flow channel. The entire manufacturing cost is lowered.

Abstract: An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.

Abstract: A micro reactor having micro flow-guiding blocks includes a first gas flow channel, a second gas flow channel and a catalytic converter. There are several flow-guiding portions disposed on the first gas flow channel. Each flow-guiding portion has micro flow-guiding blocks, flow-impact recesses, and catalytic portions. The function of the micro flow-guiding block is to guide a flowing direction of the flow toward the catalytic portion on the flow-impact recess in order to increase a possibility of contacting and chemical reaction with the catalytic portion. So, guiding the flow direction toward the catalytic portion can increase the overall reaction efficiency. More turbulence is generated to obtain a better mixing. Plus, its structure is simple.

Abstract: A method for operating a nitride-based flash memory is provided. The operation method includes pre-performing an interference reduction operation (IRO) before the routine programming operating step. Through bias arrangement of the target memory cell, charges are injected into the charge trapping layer mainly above the junction regions of the memory cell before programming so as to reset the influences caused by coupling interference issues. The operation method of this present invention not only reduces coupling interference but also afford a wider operation window.

Abstract: An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.

Abstract: A thin-film detecting device includes a plate set and a thin-film detecting portion especially for fuel cell, steam reformer and the like. This plate set has a first plate and a second plate. Each first plate has an inner surface, an outer surface, at least one channel, a gas inlet and a gas outlet. The thin-film detecting portion is disposed between the first plate and the second plate. This thin-film detecting portion is deformable and has at least one sensor. Each sensor has a connecting line extending from the sensor to a controller. About this invention, its structure is simple. It is easy to install. The exchangeability is high. And, it can be disposed on a specific position easily.

Abstract: A manufacturing method of fuel cell having micro sensors and polymer layers is disclosed. It include the following steps of: (1) depositing first polymer layer step, (2) first lithographic processing step, (3) depositing chromium layer step, (4) depositing gold layer step, (5) removing first photo-resist layer step, (6) depositing second polymer layer step, (7) second lithographic processing step, (8) plasma etching step, (9) removing second photo-resist layer step, and (10) complete step. About this invention, the polymer layers can protect the micro sensors. The micro sensors can be installed at a specific location in the flow channel. The entire manufacturing cost is lowered.

Abstract: This invention is to introduce a manufacturing method of fuel cell with integration of catalytic layer and micro sensors, which comprises following steps: manufacturing multi-hole silicon layer step, generating catalytic layer step, forming insulation layer step, integrating micro sensors step, and finalizing step. With the function of gas-diffusion layer in the multi-hole silicon wafer and multiple catalytic grains evenly spread over the inner walls of flow-way holes of the silicon wafer, a great catalytic layer can be formed effectively. Further, micro sensors properly are integrated. This invention's merits include simple structure and capabilities of simultaneously detecting temperature and humidity. Plus, it can heat up internally for a fuel cell.