Abstract: A GNSS emergency monitoring error suppression method for an alpine canyon complex environment is provided. Through three steps of GNSS optimization design of the alpine canyon complex environment, derived error suppression of emergency monitoring criteria in the alpine canyon complex environment, and error suppression measurement and result correction, GNSS measurement errors in the alpine canyons can be effectively suppressed. Through improving measurement accuracy, GNSS technology can be widely applied to the alpine canyons, outstanding advantages of high efficiency and high accuracy in a coordinate transmission process of the GNSS technology are brought into full play, and a cost is effectively reduced. Meanwhile, by processing the errors of the emergency monitoring criteria, it is possible to protect workers from on-site operation risks.

Abstract: According to example embodiments of the present disclosure, a method, device and computer program product for data backup are proposed. The method comprises: obtaining a respective current value of an attribute associated with a respective backup for at least one client in a backup system and an expected time window for performing the respective backup; determining a respective duration of the respective backup based on the respective current value; and determining a respective backup time period for performing the respective backup for the at least one client based on the respective duration and the expected time window. As such, the present solution may implement automatic backup scheduling.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes data lines; first structures located in a first region, electrically separated from each other, and including first conductive contacts coupled to the data lines; second conductive contacts located in the first region and coupled to memory elements of the apparatus; second structures located in a second region, electrically separated from each other, and including respective gates of transistors in the second region; a first dielectric material formed in the second region and including a first portion and a second portion, the first portion formed at a first side of a structure among the second structures, the second portion formed at a second side first of the structure; and a second dielectric material formed over the first structures and the second structure. A portion of the second dielectric material contacts the first portion of the first dielectric material.

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Conductive vias are formed that are individually directly electrically coupled to the another source/drain region. Conductor material is formed that is directly coupled to the one source/drain region. The conductor material is patterned in one direction to form horizontal lines of the conductor material that have a horizontal trench between immediately-adjacent of the horizontal conductor-material lines. In a self-aligned manner, digitlines are formed that are individually in individual of the trenches between the immediately-adjacent conductor-material lines.

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Conductive vias are formed that are individually directly electrically coupled to the another source/drain region. Conductor material is formed that is directly coupled to the one source/drain region. The conductor material is patterned in one direction to form horizontal lines of the conductor material that have a horizontal trench between immediately-adjacent of the horizontal conductor-material lines. In a self-aligned manner, digitlines are formed that are individually in individual of the trenches between the immediately-adjacent conductor-material lines.

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Conductive vias are formed that are individually directly electrically coupled to the another source/drain region. Conductor material is formed that is directly coupled to the one source/drain region. The conductor material is patterned in one direction to form horizontal lines of the conductor material that have a horizontal trench between immediately-adjacent of the horizontal conductor-material lines. In a self-aligned manner, digitlines are formed that are individually in individual of the trenches between the immediately-adjacent conductor-material lines.

Abstract: Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: A method used in forming an array of vertical transistors comprises forming pillars individually comprising an upper source/drain region, a channel region vertically below the upper source/drain region, and sacrificial material above the upper source/drain region. Intervening material is about the sacrificial material of individual of the pillars. The intervening material and the sacrificial material comprise different compositions relative one another. Horizontally-elongated and spaced conductive gate lines are formed individually operatively aside the channel region of the individual pillars. The sacrificial material is removed to expose the upper source/drain region of the individual pillars and thereby form an opening in the intervening material directly above the upper source/drain region of the individual pillars.

Abstract: The present application discloses a serial flash memory, including a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein the control module includes a row enable signal; and when the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. The present application further provides an address control method of a serial flash memory. In the present application, the timing requirement on the row address can be relaxed, the area of the row decoder can be reduced, and the area of the row drive circuit can be reduced.

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.

Abstract: A method used in forming an array of vertical transistors comprises forming pillars individually comprising an upper source/drain region, a channel region vertically below the upper source/drain region, and sacrificial material above the upper source/drain region. Intervening material is about the sacrificial material of individual of the pillars. The intervening material and the sacrificial material comprise different compositions relative one another. Horizontally-elongated and spaced conductive gate lines are formed individually operatively aside the channel region of the individual pillars. The sacrificial material is removed to expose the upper source/drain region of the individual pillars and thereby form an opening in the intervening material directly above the upper source/drain region of the individual pillars.

Abstract: Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.

Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

Abstract: The present application discloses a serial flash memory, including a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein the control module includes a row enable signal; and when the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. The present application further provides an address control method of a serial flash memory. In the present application, the timing requirement on the row address can be relaxed, the area of the row decoder can be reduced, and the area of the row drive circuit can be reduced.

Abstract: Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: A charge pump unit structure of a charge pump circuit includes a booster circuit unit, a positive pump transfer unit and a negative pump transfer unit. An output terminal of the booster circuit unit is connected to an input terminal of the positive pump transfer unit through a first switch circuit and to an input terminal of the negative pump transfer unit through a second switch circuit. An erase enable signal is connected to control terminals of the positive and negative pump transfer units. A first enable signal is connected to control terminals of the positive pump transfer unit and the first switch circuit. A second enable signal is connected to control terminals of the negative pump transfer unit and the second switch circuit.

Abstract: Systems, apparatuses, and methods related to epitaxial growth on semiconductor structures are described. An apparatus may include a working surface of a substrate material and a storage node connected to an active area of an access device on the working surface. The apparatus may also include a material epitaxially grown over the storage node contact to enclose a non-solid space between the storage node contact and passing sense lines.