Abstract: A reference-current generation method for flash includes first and second memory arrays separated by a word-line switching circuit. A reference-current generation circuit includes rows of reference cells, the first row parallel with the other rows of the first memory array and having the same number of columns as the other rows thereof, and the second row parallel with the other rows of the second memory array and having the same number of columns as the other rows thereof. The first reference word line of the first row is disconnected with the second reference word line of the second row. After programming, the first row enables the first memory array to create the first reference current used while performing read operation for the second memory array, and the second row enables the second memory array to create the second reference current used while performing read operation for the first memory array.

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.

Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

Abstract: A reference-current generation method for flash includes first and second memory arrays separated by a word-line switching circuit. A reference-current generation circuit includes rows of reference cells, the first row parallel with the other rows of the first memory array and having the same number of columns as the other rows thereof, and the second row parallel with the other rows of the second memory array and having the same number of columns as the other rows thereof. The first reference word line of the first row is disconnected with the second reference word line of the second row. After programming, the first row enables the first memory array to create the first reference current used while performing read operation for the second memory array, and the second row enables the second memory array to create the second reference current used while performing read operation for the first memory array.

Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

Abstract: Method of operating flash memory unit is provided. Flash memory unit includes first and second split-gate flash memory units, source and drain of first split-gate flash memory unit are connected with first and third bit lines respectively, source and drain of second split-gate flash memory unit is connected with second and third bit line respectively, first control gates of two split-gate flash memory units are connected with first control gate line, second control gates of two split-gate flash memory units are connected with second control gate line, word line gates of two split-gate flash memory units are connected with word line, method includes configuring voltages to first and third bit lines, word line, first and second control gate lines to select first storage bit in first split-gate flash memory unit and make first storage bit in to-be-read or to-be-programmed state; suspending second bit line; reading or programming first storage bit.

Abstract: A boost capacitor circuit is disclosed which includes a first nMOS transistor and a voltage doubler circuit including: a first pMOS transistor having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node; a drive inverter having an input terminal for receiving a first signal; a second pMOS transistor having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node; a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and a second nMOS transistor having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node.

Abstract: A programming verification control circuit is disclosed, including: a first decoder circuit for decoding a word line of a memory bit; a first drive circuit for receiving a first voltage and providing the first voltage to the word line of the memory bit based on a decoding result of the first decoder circuit; a second decoder circuit for decoding a control gate of the memory bit; a second drive circuit for receiving a second voltage and providing the second voltage to the control gate of the first memory bit based on a decoding result of the second decoder circuit; and a voltage equalizer for receiving the first voltage, the second voltage and a first enable signal and, in event of the first enable signal being valid, controlling the first voltage and the second voltage to be conducted. A method for controlling the programming verification control circuit is also disclosed.

Abstract: A programming verification control circuit is disclosed, including: a first decoder circuit for decoding a word line of a memory bit; a first drive circuit for receiving a first voltage and providing the first voltage to the word line of the memory bit based on a decoding result of the first decoder circuit; a second decoder circuit for decoding a control gate of the memory bit; a second drive circuit for receiving a second voltage and providing the second voltage to the control gate of the first memory bit based on a decoding result of the second decoder circuit; and a voltage equalizer for receiving the first voltage, the second voltage and a first enable signal and, in event of the first enable signal being valid, controlling the first voltage and the second voltage to be conducted. A method for controlling the programming verification control circuit is also disclosed.

Abstract: A boost capacitor circuit is disclosed which includes a first nMOS transistor and a voltage doubler circuit including: a first pMOS transistor having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node; a drive inverter having an input terminal for receiving a first signal; a second pMOS transistor having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node; a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and a second nMOS transistor having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node.

Abstract: A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

Abstract: Memory, and erasing, programming and reading method thereof are provided. In the memory, a first isolation cell, a second isolation cell and a memory cell have same structure. A first doped region of the memory cell and a second doped region of the first isolation cell are connected with a first bit line, a second doped region of the memory cell and a first doped region of the second isolation cell are connected with a second bit line. A first doped region of the first isolation cell serves as a connection terminal thereof, first and second control gate structures of the first isolation cell are connected together to serve as a control terminal thereof, a second doped region of the second isolation cell serves as a connection terminal thereof, first and second control gate structures of the second isolation cell are connected together to serve as a control terminal thereof.

Abstract: Memory, and erasing, programming and reading method thereof are provided. In the memory, a first isolation cell, a second isolation cell and a memory cell have same structure. A first doped region of the memory cell and a second doped region of the first isolation cell are connected with a first bit line, a second doped region of the memory cell and a first doped region of the second isolation cell are connected with a second bit line. A first doped region of the first isolation cell serves as a connection terminal thereof, first and second control gate structures of the first isolation cell are connected together to serve as a control terminal thereof, a second doped region of the second isolation cell serves as a connection terminal thereof, first and second control gate structures of the second isolation cell are connected together to serve as a control terminal thereof.

Abstract: A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

Abstract: Charge pump system and memory are provided. The system includes: a first enabling control unit, adapted to delay at least one start-up signal of the system to obtain and output an oscillating enabling signal after receiving the at least one start-up signal and a voltage boosting enabling signal; a second enabling control unit, adapted to delay the oscillating enabling signal to obtain and output a charge pump enabling signal after receiving the oscillating enabling signal and the voltage boosting enabling signal; a clock oscillating unit, adapted to generate a clock signal after receiving the oscillating enabling signal; and at least one charge pump cell, adapted to output a boosting voltage after receiving the charge pump enabling signal and the clock signal, obtain the voltage boosting enabling signal based on the boosting voltage, and output the voltage boosting enabling signal. Power consumption of the system in a start-up process is reduced.

Abstract: A semiconductor device comprises a substrate, a word line, an insulation material, and an etch stop material. The substrate comprises a pillar that may comprise an active area. The word line is formed in the substrate. The insulation material is formed on the word line. The etch stop material is formed on the insulating material and around the pillar.

Abstract: The present invention discloses a flash-memory low-speed read mode control circuit, which comprises a charge pump, a first voltage division circuit composed of two resistors and a first switch interconnected in series, and a second voltage division circuit composed of two capacitors interconnected in series. The first switch is used for switching between the data read mode of the low-speed read mode and the charge pump electric-leakage mode. In the data read mode, a first component voltage formed by the two resistors is fed back to the input terminal of the charge pump through a comparator, an NAND gate and a buffer, making a stable value of the output voltage of the charge pump proportional to the first component voltage.

Abstract: The present invention discloses a flash-memory low-speed read mode control circuit, which comprises a charge pump, a first voltage division circuit composed of two resistors and a first switch interconnected in series, and a second voltage division circuit composed of two capacitors interconnected in series. The first switch is used for switching between the data read mode of the low-speed read mode and the charge pump electric-leakage mode. In the data read mode, a first component voltage formed by the two resistors is fed back to the input terminal of the charge pump through a comparator, an NAND gate and a buffer, making a stable value of the output voltage of the charge pump proportional to the first component voltage.

Abstract: Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include use of sulfur dioxide and a halogen-based compound to form a trimmed pattern of a patterning material, such as a resist material, at a critical dimension with low feature width roughness, with low space width roughness, without excessive height loss, and without substantial irregularities in the elevational profile, as compared to trimmed features formed using conventional chemistries and trimming methods.