Abstract: A computerized simulation validating method for a full-scale distribution network single phase-to-ground fault test is implemented by simulating a full-scale test system with external quantities being controlled to be conformant and validating the full-scale distribution network single phase-to-ground fault test based on a conformance check result between the internal quantities of the field testing and the internal quantities of the simulation testing. The simulation validating method for a full-scale distribution network single phase-to-ground fault test improves normalization and conformance of the full-scale distribution network ground fault test. The computerized simulation validating system, apparatus, and medium for a full-scale distribution network single phase-to-ground fault test also achieve the benefits noted above.

Abstract: Provided are a display substrate and a detection method therefor, and a display apparatus. Compensation sub-circuits that are in one-to-one correspondence with each stage of a shift register are arranged in a gate driving circuit, and a first capacitor in each compensation sub-circuit is thus charged under the control of a detection input circuit when each stage of the shift register outputs a signal stage by stage; and an output control circuit is used to disconnect the compensation sub-circuit from a pull-up node of the corresponding stage of the shift register. The triggering of each stage of the shift register is stopped after each stage of the shift register (CR(n)) completes outputting, and the output control circuit provides a signal of a first power voltage end to the pull-up node of the corresponding stage of the shift register under the control of a second control end and the first capacitor.

Abstract: A GOA circuit and a display panel are proposed. An inverting control module controls the voltage level of the first node to be opposite to the voltage level of the second node under the control of an (n+1)th-stage clock signal, so that a DC path between a constant high voltage terminal and a first constant low voltage terminal is not formed. When a first node is at the low voltage level, the voltage applied on the second node transitions from the low voltage level to high voltage level. Accordingly, the second node is constantly at the high voltage level at the pull-down maintenance stage in the GOA circuit, and the nth-stage gate-driven signal terminal is still at the low voltage level. In this way, the GOA circuit will not become ineffective.

Abstract: A method for optimizing HDR video display processing comprises: acquiring original video stream data; decoding the original video stream data to obtain metadata and image frame data of each image frame; in an m-th iteration, for each image frame, according to a characteristic parameter of a target display panel and the metadata, performing HDR processing on the image frame data by using an HDR video display processing algorithm, to obtain the image frame data subjected to HDR processing and corresponds to the original video stream data in the m-th iteration; and according to a playing display detection result, on the target display panel, of the image frame data that has been subjected to HDR processing and is obtained in the m-th iteration, optimizing an algorithm used in an (m+1)th iteration until the optimization of the HDR video display processing algorithm is completed.

Abstract: The present disclosure provides an OLED display panel and a method for detecting the OLED display panel, and a display device. The OLED display panel includes a base substrate including a display area and a non-display area surrounding the display area and having a first region adjacent to the display area. The display area includes a drive signal line and a power supply voltage signal line both extending from the display area to the first region. The drive signal line includes, in the first region, a first section of wiring at an anode layer, the power supply voltage signal line includes, in the first region, a second section of wiring at a gate metal layer, and parts of the drive signal line and the power supply voltage signal line in the display area are located at a source-drain metal layer.

Abstract: Embodiments of the present disclosure provide an array substrate comprising a base substrate, a buffer layer disposed on the base substrate, an interlayer dielectric layer disposed on the buffer layer, and a protection layer disposed on the interlayer dielectric layer, where the array substrate further comprises a plurality of first test units and a plurality of test leads. The plurality of test leads are connected to the plurality of first test units in a one-to-one correspondence, and the plurality of test leads are disposed in at least two different layers. A method for manufacturing an array substrate, a display panel, and a display device are further provided.

Abstract: The present disclosure provides a method for detecting a display substrate and a device for detecting a display substrate. The method includes: exciting a threshold voltage of a driving transistor in each pixel driving circuit in the display substrate, so that the threshold voltage of the driving transistor with a shifted threshold voltage is further shifted; inputting a detection signal to each pixel driving circuit in the display substrate, where the detection signal is a signal enabling the pixel driving circuit to operate normally; and judging whether the display substrate is normal or not according to the voltage output by each pixel driving circuit.

Abstract: A sterilization structure, a sterilization board, and a display device are disclosed. The sterilization structure includes an active layer, wherein, one surface of the active layer has an exposed region, and a material of the active layer includes a laser-induced graphene material.

Abstract: Provided are a display substrate and a detection method therefor, and a display apparatus. Compensation sub-circuits that are in one-to-one correspondence with each stage of a shift register are arranged in a gate driving circuit, and a first capacitor in each compensation sub-circuit is thus charged under the control of a detection input circuit when each stage of the shift register outputs a signal stage by stage; and an output control circuit is used to disconnect the compensation sub-circuit from a pull-up node of the corresponding stage of the shift register. The triggering of each stage of the shift register is stopped after each stage of the shift register (CR(n)) completes outputting, and the output control circuit provides a signal of a first power voltage end to the pull-up node of the corresponding stage of the shift register under the control of a second control end and the first capacitor.

Abstract: Disclosed are an array substrate, a method for fabricating the same, a display panel, and a display device, and the array substrate includes: an underlying substrate, and gate lines and data lines located on the underlying substrate, and intersecting with each other, a layer where the gate lines are located is between a layer where the data lines are located, and the underlying substrate; and the array substrate further includes a buffer layer located between the underlying substrate and the layer where the gate lines are located; and the buffer layer includes a plurality of through-holes, where orthographical projections of the through-holes onto the underlying substrate cover orthographical projections of the areas where the gate lines intersect with the data lines, onto the underlying substrate.

Abstract: The present disclosure provides a positive photoresist composition including a major adhesive material and a photosensitizer, wherein the photoresist composition further includes a photoisomerizable compound which would be converted into an ionic structure with an increased degree of molecular polarity after ultraviolet irradiation. The formation of the ionic structure with increased polarity of the molecule reduces the adhesion between the positive photoresist and the organic film layer, facilitates stripping after formation of the via, and improves the product rate of pass. Further, the present disclosure provides a via-forming method using the positive resist composition, a display substrate including the via formed by the via-forming method, and a display device including the display substrate.

Abstract: The present invention relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a first electrode layer. The first electrode layer may include an indium tin oxide layer and a planarization layer. The indium tin oxide layer is disposed on a substrate and includes indium tin oxide particles; the planarization layer is disposed on a side of the indium tin oxide layer away from the substrate, and fills at least part of gaps between the indium tin oxide particles, and the planarization layer can conduct electricity.

Abstract: A display substrate includes a base substrate; and a single pixel definition layer on the base substrate defining a plurality of subpixel apertures. The single pixel definition layer includes a plurality of hydrophobic particles dispersed in a main body for enhancing hydrophobicity of a portion of the single pixel definition layer.

Abstract: A method of detecting threshold voltage shift and a threshold voltage shift detection device are provided. The method is applied to a pixel driving circuit which I is electrically coupled to a control line, a voltage line and a detection node, respectively. The method includes: in a detection cycle including a setting phase and a detection phase, in the setting phase, controlling a transistor included in the pixel driving circuit to be in a biased state; in the detection phase, providing a preset control voltage signal to the control line, providing a preset voltage signal to the voltage line, and determining a threshold voltage shift state of the transistor according to an electric potential of the detection node.

Abstract: The disclosure relates to a thin film transistor. The thin film transistor may include a substrate, an active layer on the substrate, a gate on the active layer, and a source and a drain. The active layer may include a first conducting region, a second conducting region, and a channel region between the first conducting region and the second conducting region. An orthographic projection of the source and an orthographic projection of the drain on the substrate may cover at least an orthographic projection of a first conducting region and an orthographic projection of a second conducting region on the substrate.

Abstract: A degradable and absorbable hemostatic fiber material, a preparation method therefor, and a hemostatic fiber article thereof. The carboxylation degree of the hemostatic fiber material is 10-25%, and the polymerization degree of the hemostatic fiber material is 10-250. The hemostatic fiber material comprises fiber filaments, the linear density of the fiber filament being 0.8-4.5 dtex, and the dry strength of the fiber filament being 10-150 cN/tex. The degradable and absorbable hemostatic fiber material has a higher carboxylation degree and a lower polymerization degree, while the strength and completeness of the fiber filament can be well maintained, such that the hemostatic effect is better and the hemostasis is faster. Further, the hemostatic fiber material can be degraded and absorbed, and thus is safer.

Abstract: The present disclosure is related to a thin film transistor. The thin film transistor may include an active layer; a gate insulating layer on the active layer; and a gate and a plurality of metal films on the gate insulating layer. The plurality of metal films may be spaced apart from the gate, and insulated from the gate and the active layer.

Abstract: The present disclosure provides a method for detecting a display substrate and a device for detecting a display substrate. The method includes: exciting a threshold voltage of a driving transistor in each pixel driving circuit in the display substrate, so that the threshold voltage of the driving transistor with a shifted threshold voltage is further shifted; inputting a detection signal to each pixel driving circuit in the display substrate, where the detection signal is a signal enabling the pixel driving circuit to operate normally; and judging whether the display substrate is normal or not according to the voltage output by each pixel driving circuit.

Abstract: A thin film transistor, a display panel and a preparation method thereof and a display apparatus are provided. The thin film transistor includes: a substrate; a gate metal located on a side of the substrate; a gate insulating layer located on a side of the gate metal away from the substrate; an active layer located on a side of the gate insulating layer away from the substrate; a first metal oxide and a second metal oxide which are located on a side of the active layer away from the substrate and are arranged on a same layer; and a source metal and a drain metal which are located on sides of the first metal oxide and the second metal oxide away from the substrate and are arranged in a same layer.

Abstract: The present disclosure provides a photoresist composition, a pixel definition layer, a display substrate and a method for preparing the same, and a display device. The photoresist composition includes: 5 to 25 wt % of polymethacrylate; 1 to 15 wt % of a lyophobic compound; 1 to 5 wt % of a temperature sensitive polymer; 0.5 to 2 wt % of a photoinitiator; and 0.1 to 1 wt % of a monomer.