Patents by Inventor Guenole Jan

Guenole Jan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10115892
    Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 × to 30 × that of the amorphous layer. The uppermost seed (template) layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is Ta or TaN, for example. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded memory devices, or read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M may be B.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: October 30, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Jodi Mari Iwata, Vignesh Sundar, Luc Thomas, Yu-Jen Wang, Sahil Patel
  • Patent number: 10102896
    Abstract: A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 16, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Po-Kang Wang, John De Brosse, Yuan-Jen Lee
  • Publication number: 20180267128
    Abstract: A ferromagnetic resonance (FMR) measurement system is disclosed with a waveguide transmission line (WGTL) connected at both ends to a mounting plate having an opening through which the WGTL is suspended. While the WGTL bottom surface contacts a portion of magnetic film on a whole wafer, a plurality of microwave frequencies is sequentially transmitted through the WGTL. Simultaneously, a magnetic field is applied to the contacted region thereby causing a FMR condition in the magnetic film. After RF output is transmitted through or reflected from the WGTL to a RF detector and converted to a voltage signal, effective anisotropy field, linewidth, damping coefficient, and/or inhomogeneous broadening are determined based on magnetic field intensity, microwave frequency and voltage output. A plurality of measurements is performed by controllably moving the WGTL or wafer and repeating the simultaneous application of microwave frequencies and magnetic field at additional preprogrammed locations on the magnetic film.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 20, 2018
    Inventors: Santiago Serrano Guisan, Luc Thomas, Son Le, Guenole Jan
  • Publication number: 20180269387
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a continuous or discontinuous metal (M) or MQ alloy layer within the FL reacts with scavenged oxygen to form a partially oxidized metal or alloy layer that enhances PMA and maintains acceptable RA. M is one of Mg, Al, B, Ca, Ba, Sr, Ta, Si, Mn, Ti, Zr, or Hf, and Q is a transition metal, B, C, or Al. Methods are also provided for forming composite free layers where interfacial perpendicular anisotropy is generated therein by contact of the free layer with oxidized materials.
    Type: Application
    Filed: May 7, 2018
    Publication date: September 20, 2018
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong, Po-Kang Wang
  • Publication number: 20180269385
    Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 20, 2018
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong
  • Patent number: 10014465
    Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer has an interface with a tunnel barrier and a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or CoXFeYNiZLW wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing at about 400° C. thereby promoting BCC structure growth in the oxide layer. As a result, free layer PMA is enhanced and maintained to yield improved thermal stability.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: July 3, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Mari Iwata
  • Publication number: 20180175287
    Abstract: A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic %, and an adjoining second layer with a boron content from 1 to 20 atomic %. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 1 to 10 Angstroms and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400° C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 21, 2018
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Po-Kang Wang
  • Patent number: 9966529
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, metal clusters are formed in the FL and are subsequently partially or fully oxidized by scavenging oxygen to generate additional FL/oxide interfaces that enhance PMA, provide an acceptable resistance x area (RA) value, and preserve the magnetoresistive ratio. In other embodiments, a continuous or discontinuous metal (M) or MQ alloy layer within the FL reacts with scavenged oxygen to form a partially oxidized metal or alloy layer that enhances PMA and maintains acceptable RA. M is one of Mg, Al, B, Ca, Ba, Sr, Ta, Si, Mn, Ti, Zr, or Hf, and Q is a transition metal, B, C, or Al.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 8, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong, Po-Kang Wang
  • Publication number: 20180026179
    Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30× that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 25, 2018
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
  • Publication number: 20180005746
    Abstract: An improved magnetic tunnel junction with two oxide interfaces on each side of a ferromagnetic layer (FML) leads to higher PMA in the FML. The novel stack structure allows improved control during oxidation of the top oxide layer. This is achieved by the use of a FML with a multiplicity of ferromagnetic sub-layers deposited in alternating sequence with one or more non-magnetic layers. The use of non-magnetic layers each with a thickness of 0.5 to 10 Angstroms and with a high resputtering rate provides a smoother FML top surface, inhibits crystallization of the FML sub-layers, and reacts with oxygen to prevent detrimental oxidation of the adjoining ferromagnetic sub-layers. The FML can function as a free or reference layer in an MTJ. In an alternative embodiment, the non-magnetic material such as Mg, Al, Si, Ca, Sr, Ba, and B is embedded by co-deposition or doped in the FML layer.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Luc Thomas, Guenole Jan, Ru-Ying Tong
  • Patent number: 9842988
    Abstract: A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic %, and an adjoining second layer with a boron content from 1 to 20 atomic %. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 1 to 10 Angstroms and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400° C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: December 12, 2017
    Assignee: Headway Technologies, Inc.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Po-Kang Wang
  • Publication number: 20170352395
    Abstract: A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 7, 2017
    Inventors: Guenole Jan, Po-Kang Wang, John De Brosse, Yuan-Jen Lee
  • Patent number: 9805816
    Abstract: An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. When a voltage is applied across the magnetic OTP memory cell, the resistance of the MTJ stack and the gating transistor form a voltage divider to apply a large voltage across the MTJ stack to breakdown the tunnel barrier to short the fixed layer to the free layer. The integrated circuit has multiple MRAM arrays configured such that each of the multiple MRAM arrays have performance and density criteria that match MOS transistor based memory including SRAM, DRAM, and flash memory. The integrated circuit may include a functional logic unit connected with the magnetic OTP memory arrays and the MRAM arrays for providing digital data storage.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: October 31, 2017
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Po-Kang Wang, Yuan-Jen Lee, Jian Zhu, Huanlong Liu
  • Patent number: 9780299
    Abstract: A seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a seed layer such as Mg where the seed layer has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed layer is a template layer that is NiCr or NiFeCr. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited. The seed layer stack may include a bottommost Ta or TaN buffer layer.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 3, 2017
    Assignee: Headway Technologies, Inc.
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
  • Publication number: 20170256703
    Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed (template) layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is one or more of Ta, TaN, Zr, ZrN, Nb, NbN, Mo, MoN, TiN, W, WN, and Ru. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.
    Type: Application
    Filed: May 19, 2017
    Publication date: September 7, 2017
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Jodi Mari Iwata, Vignesh Sundar, Luc Thomas, Yu-Jen Wang, Sahil Patel
  • Patent number: 9747965
    Abstract: A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 29, 2017
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Po-Kang Wang, John De Brosse, Yuan-Jen Lee
  • Publication number: 20170186472
    Abstract: A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Guenole Jan, Po-Kang Wang, John De Brosse, Yuan-Jen Lee
  • Patent number: 9673385
    Abstract: A seed layer stack with a smooth top surface having a peak to peak roughness of about 0.5 nm over a range of 100 nm is formed by sputter depositing an X layer such as Mo on a Ni layer where the X layer has one or both of a larger bond energy and a greater atomic number than Ni. A (Ni/X)m laminate is formed and then an uppermost NiCr seed layer is deposited to enhance perpendicular magnetic anisotropy (PMA) in an overlying ferromagnetic layer. A <111> NiCr crystal structure promotes <111> texture in the ferromagnetic layer. X layers serve as a diffusion barrier to Ta migration from a bottom electrode and have good lattice matching with the adjoining Ni layer and uppermost NiCr layer. As a result of the smooth seed layer stack in a magnetic tunnel junction (MTJ), MTJ properties are improved and more reproducible.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 6, 2017
    Assignee: Headway Technologies, Inc.
    Inventors: Huanlong Liu, Ru-Ying Tong, Guenole Jan
  • Publication number: 20170148977
    Abstract: A seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a seed layer such as Mg where the seed layer has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed layer is a template layer that is NiCr or NiFeCr. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited. The seed layer stack may include a bottommost Ta or TaN buffer layer.
    Type: Application
    Filed: November 23, 2015
    Publication date: May 25, 2017
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
  • Publication number: 20170117456
    Abstract: A magnetic element is disclosed wherein a composite seed layer such as TaN/Mg enhances perpendicular magnetic anisotropy (PMA) in an overlying magnetic layer that may be a reference layer, free layer, or dipole layer. The first seed layer is selected from one or more of Ta, Zr, Nb, TaN, ZrN, NbN, and Ru. The second seed layer is selected from one or more of Mg, Sr, Ti, Al, V, Hf, B, and Si. A growth promoting layer made of NiCr or an alloy thereof is inserted between the seed layer and magnetic layer. In some embodiments, a first composite seed layer/NiCr stack is formed below the reference layer, and a second composite seed layer/NiCr stack is formed between the free layer and a dipole layer. The magnetic element has thermal stability to at least 400° C.
    Type: Application
    Filed: November 7, 2016
    Publication date: April 27, 2017
    Inventors: Guenole Jan, Ru-Ying Tong