Abstract: In an embodiment a reflector optical system includes a reflector body having a rotational symmetry about a longitudinal axis and including a first reflector optic portion having a substantially concave shape and a second reflector optic portion extending along the longitudinal axis, the first reflector optic portion facing the second reflector optic portion, wherein the first reflector optic portion includes a plurality of first reflective surfaces and the second reflector optic portion includes a plurality of second reflective surfaces in spaced light-receiving relation to the plurality of first reflective surfaces.

Abstract: An automotive solid-state headlamp includes a lamp body extending in a longitudinal direction, the lamp body having a rear base portion and a front portion and including a support member and a light-transmissive housing, a plurality of solid-state light sources arranged on the support member at the rear base portion of the lamp body, a drive circuitry electrically coupled to the light sources and arranged at the rear base portion of the lamp body and configured to operate the plurality of light sources when energized and reflector optics arranged at the front portion, wherein the solid-state light sources are configured to emit light towards the reflector optics, the reflector optics including a first reflector optic portion and a second reflector optic portion and wherein each of a plurality of first reflective surfaces disposed on the first reflector optic portion extend in an annular region around the longitudinal direction from the plurality of solid-state light sources towards the first reflector optic p

Abstract: In an embodiment an automotive solid-state headlamp includes a lamp body extending in a longitudinal direction, the lamp body having a rear base portion and a front portion and including a support member disposed in a light-transmissive housing, a plurality of solid-state light sources arranged on the support member at the rear base portion of the lamp body, and a drive circuitry electrically coupled to the light sources and arranged at the rear base portion of the lamp body and configured to operate the plurality of light sources when energized, wherein the plurality of light sources, when energized, are configured to cause the solid-state lamp to emit, through the light-transmissive housing (a) a luminous flux of at least 1500 lumens +/?10% when energized with a 13.2 Volt test voltage, or of at least 1750 lumens +/?10% when energized with a 28 Volt test voltage, or (b) a luminous flux of at least 1350 lumens +/?10% when energized with a 13.

Abstract: In an embodiment a reflector optical system includes a reflector body having a rotational symmetry about a longitudinal axis and including a first reflector optic portion having a substantially concave shape and a second reflector optic portion extending along the longitudinal axis, the first reflector optic portion facing the second reflector optic portion, wherein the first reflector optic portion includes a plurality of first reflective surfaces and the second reflector optic portion includes a plurality of second reflective surfaces in spaced light-receiving relation to the plurality of first reflective surfaces.

Abstract: The invention relates to a method of identifying or producing an aptamer, and a reagent comprising a nucleic acid ligand capable of binding a target sample, wherein the nucleic acid ligand comprises at least one nucleobase modified to contain an azide-alkyne chemical group.

Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Abstract: A mechanism is provided for verifying design modifications to a simulation design unit included within a simulation model of an integrated electronic device. A modified description is received of a simulation design unit that failed to meet an expected physical property value during an initial simulation of the entire integrated electronic device. A simulation of the simulation design unit is executed using a list of identified input signals from a trace file. The trace file is generated during the initial simulation and indicates state values for the list of identified input signals. A determination is made as to whether the simulation of the simulation design unit fails to meet the expected physical property value. An indication is generated that modifications made to an initial description of the simulation design unit are successful in response to the simulation of the simulation design unit meeting the expected physical property value.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.

Abstract: A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.

Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Abstract: A method and apparatus is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.

Abstract: A device and method for storing information including an array of memory cells organized in bitlines and wordlines. The bitlines are subdivided in sections of wordlines and the sectioned bitlines are connected to a global bitline by a connector. The connector is made bidirectional and uses the high order part of the wordline addresses for this section of bitlines as a disable reset command. The reset stays active for unselected portions, compensating leakage of a mass of unselected cells which could disturb valid read signals.

Abstract: A device and method for storing information including an array of memory cells organized in bitlines and wordlines. The bitlines are subdivided in sections of wordlines and the sectioned bitlines are connected to a global bitline by a connector. The connector is made bidirectional and uses the high order part of the wordline addresses for this section of bitlines as a disable reset command. The reset stays active for unselected portions, compensating leakage of a mass of unselected cells which could disturb valid read signals.

Abstract: The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.

Abstract: The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.

Abstract: The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.

Abstract: The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.