Abstract: The present invention relates to compounds according to general formula (I), pharmaceutical compositions comprising compounds according to general formula (I) and the use of the compounds for the treatment of a bacterial infection, particularly for use as an antibiotic.

Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Abstract: A mechanism is provided for verifying design modifications to a simulation design unit included within a simulation model of an integrated electronic device. A modified description is received of a simulation design unit that failed to meet an expected physical property value during an initial simulation of the entire integrated electronic device. A simulation of the simulation design unit is executed using a list of identified input signals from a trace file. The trace file is generated during the initial simulation and indicates state values for the list of identified input signals. A determination is made as to whether the simulation of the simulation design unit fails to meet the expected physical property value. An indication is generated that modifications made to an initial description of the simulation design unit are successful in response to the simulation of the simulation design unit meeting the expected physical property value.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.

Abstract: The invention concerns a fuel cell comprising an anode chamber, a cathode chamber and a cavity for the electrolytic space, as well as combustion gas supply conduits and carbon dioxide and water discharge conduits for the anode chamber, and, for the cathode chamber, oxygen and carbon dioxide supply conduits and discharge conduits for residual oxygen and residual carbon dioxide. The anode chamber and the cathode chamber receive a metal sponge, the cathode chamber housing a metal or ceramic sponge. Said fuel cell is subdivided into an anode chamber, an outer cathode chamber and a median cathode chamber, separate cavities for electrolytic space located between the anode chamber and the median cathode chamber and the median cathode chamber and the outer cathode chamber.

Abstract: The invention concerns a fuel cell comprising an anode chamber, a cathode chamber and a cavity for the electrolytic space, as well as combustion gas supply conduits and carbon dioxide and water discharge conduits for the anode chamber, and, for the cathode chamber, oxygen and carbon dioxide supply conduits and discharge conduits for residual oxygen and residual carbon dioxide. The anode chamber and the cathode chamber receive a metal sponge, the cathode chamber housing a metal or ceramic sponge. Said fuel cell is subdivided into an anode chamber, an outer cathode chamber and a median cathode chamber, separate cavities for electrolytic space located between the anode chamber and the median cathode chamber and the median cathode chamber and the outer cathode chamber.

Abstract: A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.

Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Abstract: A method and apparatus is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.

Abstract: A rotatably driveable work tool (1) of a motor-driven work apparatus has, at a front end (2, 3), an end plate (5, 6) lying perpendicularly to a rotational axis (4). The end plate (5, 6) has an outer diameter (DR) which is less than a flight circular diameter (DF) of the work tool (1). The end plate (5, 6) is configured as a roll-up protective ring (8) which extends in a radial direction (14) from an inner diameter (DI) to the outer diameter (DR). The roll-up protective ring has an axially-extending component from the work tool (1) outwardly.

Abstract: A device and method for storing information including an array of memory cells organized in bitlines and wordlines. The bitlines are subdivided in sections of wordlines and the sectioned bitlines are connected to a global bitline by a connector. The connector is made bidirectional and uses the high order part of the wordline addresses for this section of bitlines as a disable reset command. The reset stays active for unselected portions, compensating leakage of a mass of unselected cells which could disturb valid read signals.

Abstract: A portable handheld work apparatus, such as a motorized cultivator (1) or the like, includes a frame (2) which extends essentially in the longitudinal direction (21) of the work apparatus. A drive motor (3) is fixed at one end (22) of the frame (2) and a work tool is driven by this drive motor. The opposite-lying end (23) includes at least a handle (7, 8) for guiding the work apparatus during the operation thereof. In order to make possible an ergonomic work posture of the operator, the handle (7, 8) lies facing away upwardly from the ground surface (42) in the work position of the motorized work apparatus. The work position is a position in which the work tool lies on the ground surface (42) to be worked.

Abstract: A device and method for storing information including an array of memory cells organized in bitlines and wordlines. The bitlines are subdivided in sections of wordlines and the sectioned bitlines are connected to a global bitline by a connector. The connector is made bidirectional and uses the high order part of the wordline addresses for this section of bitlines as a disable reset command. The reset stays active for unselected portions, compensating leakage of a mass of unselected cells which could disturb valid read signals.

Abstract: The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.

Abstract: The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.

Abstract: The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.

Abstract: The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.