Patents by Inventor Guido Albermann
Guido Albermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881425Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.Type: GrantFiled: October 18, 2022Date of Patent: January 23, 2024Assignee: NXP B.V.Inventors: Antonius Hendrikus Jozef Kamphuis, Guido Albermann, Johannes Cobussen
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Publication number: 20230061529Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.Type: ApplicationFiled: October 18, 2022Publication date: March 2, 2023Inventors: Antonius Hendrikus Jozef Kamphuis, Guido Albermann, Johannes Cobussen
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Patent number: 11508606Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.Type: GrantFiled: November 5, 2019Date of Patent: November 22, 2022Assignee: NXP B.V.Inventors: Antonius Hendrikus Jozef Kamphuis, Guido Albermann, Johannes Cobussen
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Publication number: 20210305095Abstract: A semiconductor wafer having a plurality of die is attached to a support structure. The semiconductor wafer includes an active layer over a silicon layer, wherein the active layer is at a top side, and a bottom side exposes the silicon layer. While the wafer is attached to the support structure, an infrared laser beam is focused through a portion of the silicon layer to create a modification region along saw lanes located between neighboring die of the plurality of die. Afterwards, a metal layer is formed on the exposed silicon layer at the bottom side of the semiconductor wafer. The metal layer is attached to an expansion tape, and the wafer is singulated by extending the expansion tape to separate the die of the plurality of die along the saw lane. A first singulated die of the plurality of die is packaged to form a packaged semiconductor device.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Sascha Moeller, Guido Albermann, Michael Zernack
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Publication number: 20210134647Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.Type: ApplicationFiled: November 5, 2019Publication date: May 6, 2021Inventors: Antonius Hendrikus Jozef Kamphuis, Guido Albermann, Johannes Cobussen
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Patent number: 10896878Abstract: A saw bow is provided and designed such that the conductors of the saw bow will break at a predictable location when using modern dicing techniques. This results in a break in the circuit provided by the saw bow, with any exposed conductors not being on the die side. Further, by providing a known breaking point in the saw bow, modern dicing techniques such as plasma dicing can be used, thereby allowing for the saw lane to be made narrower, which will in turn increase the number of wafers that can be included on a wafer.Type: GrantFiled: June 18, 2019Date of Patent: January 19, 2021Assignee: NXP B.V.Inventors: Antonius Hendrikus Jozef Kamphuis, Johannes Cobussen, Christian Zenz, Guido Albermann
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Publication number: 20200402918Abstract: A saw bow is provided and designed such that the conductors of the saw bow will break at a predictable location when using modern dicing techniques. This results in a break in the circuit provided by the saw bow, with any exposed conductors not being on the die side. Further, by providing a known breaking point in the saw bow, modern dicing techniques such as plasma dicing can be used, thereby allowing for the saw lane to be made narrower, which will in turn increase the number of wafers that can be included on a wafer.Type: ApplicationFiled: June 18, 2019Publication date: December 24, 2020Applicant: NXP B.V.Inventors: Antonius Hendrikus Jozef Kamphuis, Johannes Cobussen, Christian Zenz, Guido Albermann
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Patent number: 10347534Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.Type: GrantFiled: September 12, 2017Date of Patent: July 9, 2019Assignee: NXP B.V.Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Michael Zernack, Leo M. Higgins, III
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Publication number: 20190080963Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.Type: ApplicationFiled: September 12, 2017Publication date: March 14, 2019Inventors: Martin LAPKE, Hartmut Buenning, Sascha MOELLER, Guido ALBERMANN, Michael ZERNACK, Leo M. HIGGINS, III
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Patent number: 9847258Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.Type: GrantFiled: September 30, 2015Date of Patent: December 19, 2017Assignee: NXP B.V.Inventors: Thomas Rohleder, Hartmut Buenning, Guido Albermann, Sascha Moeller, Martin Lapke
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Patent number: 9812361Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.Type: GrantFiled: March 11, 2014Date of Patent: November 7, 2017Assignee: NXP B.V.Inventors: Hartmut Buenning, Sascha Moeller, Guido Albermann, Martin Lapke, Thomas Rohleder
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Publication number: 20170092540Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Thomas Rohleder, Hartmut Buenning, Guido Albermann, Sascha Moeller, Martin Lapke
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Patent number: 9601437Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.Type: GrantFiled: September 9, 2014Date of Patent: March 21, 2017Assignee: NXP B.V.Inventors: Guido Albermann, Sascha Moeller, Thomas Rohleder, Martin Lapke, Hartmut Buenning
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Publication number: 20160172243Abstract: One example discloses a system for wafer material removal, including: a wafer structures map, identifying a first device structure having a first location and a second device structure having a second location; a material removal controller, coupled to the structures map, and having a material removal beam power level output signal and a material removal beam on/off status output signal; wherein the material removal controller is configured to select a first material removal beam power level and a first material removal beam on/off status corresponding to the first location; and wherein the material removal controller is configured to select a second material removal beam power level and a second material removal beam on/off status corresponding to the second location. Another example discloses an article of manufacture comprises at least one non-transitory, tangible machine readable storage medium containing executable machine instructions for wafer material removal.Type: ApplicationFiled: December 11, 2014Publication date: June 16, 2016Inventors: Sascha Moeller, Thomas Rohleder, Guido Albermann, Martin Lapke, Hartmut Buenning
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Patent number: 9349645Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.Type: GrantFiled: October 16, 2013Date of Patent: May 24, 2016Assignee: NXP B.V.Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Heiko Backer
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Publication number: 20160071770Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.Type: ApplicationFiled: September 9, 2014Publication date: March 10, 2016Inventors: Guido Albermann, Sascha Moeller, Thomas Rohleder, Martin Lapke, Hartmut Buenning
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Publication number: 20150104931Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.Type: ApplicationFiled: October 16, 2013Publication date: April 16, 2015Applicant: NXP B.V.Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Heiko Backer
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Publication number: 20150069578Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.Type: ApplicationFiled: March 11, 2014Publication date: March 12, 2015Applicant: NXP B.V.Inventors: Hartmut BUENNING, Sascha MOELLER, Guido ALBERMANN, Martin LAPKE, Thomas ROHLEDER
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Patent number: 8895363Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.Type: GrantFiled: March 15, 2013Date of Patent: November 25, 2014Assignee: NXP B.V.Inventors: Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Michael Zernack
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Publication number: 20140264768Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: NXP B. V.Inventors: Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Michael Zernack