Patents by Inventor Guido Albermann

Guido Albermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High die strength semiconductor wafer processing method and system
    Patent number: 8809166
    Abstract: Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 19, 2014
    Assignee: NXP B.V.
    Inventors: Hartmut Buenning, Sascha Moeller, Martin Lapke, Guido Albermann, Thomas Rohleder
  • HIGH DIE STRENGTH SEMICONDUCTOR WAFER PROCESSING METHOD AND SYSTEM
    Publication number: 20140179083
    Abstract: Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: NXP B.V.
    Inventors: HARTMUT BUENNING, SASCHA MOELLER, MARTIN LAPKE, GUIDO ALBERMANN, THOMAS ROHLEDER
  • Integrated circuits on a wafer and method for separating integrated circuits on a wafer
    Patent number: 8415769
    Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: April 9, 2013
    Assignee: NXP B.V.
    Inventors: Heimo Scheucher, Guido Albermann, David Ceccarelli
  • Integrated Circuits On A Wafer and Method For Separating Integrated Circuits On A Wafer
    Publication number: 20100270655
    Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).
    Type: Application
    Filed: July 10, 2008
    Publication date: October 28, 2010
    Applicant: NXP B.V.
    Inventors: Heimo Scheucher, Guido Albermann, David Ceccarelli