Patents by Inventor Guido Jozef Maria Dormans
Guido Jozef Maria Dormans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11670394Abstract: A temperature exposure detection system includes a plurality of nonvolatile memory cells. The memory includes memory read circuitry for reading the plurality of memory cells to determine a data retention error rate of the plurality of memory cells. The temperature exposure detection system determines a temperature exposure of the system based on the determined data retention error rate.Type: GrantFiled: August 18, 2021Date of Patent: June 6, 2023Assignee: NXP B.V.Inventors: Michiel Jos van Duuren, Guido Jozef Maria Dormans, Anirban Roy
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Publication number: 20230056133Abstract: A temperature exposure detection system includes a plurality of nonvolatile memory cells. The memory includes memory read circuitry for reading the plurality of memory cells to determine a data retention error rate of the plurality of memory cells. The temperature exposure detection system determines a temperature exposure of the system based on the determined data retention error rate.Type: ApplicationFiled: August 18, 2021Publication date: February 23, 2023Inventors: Michiel Jos van Duuren, Guido Jozef Maria Dormans, Anirban Roy
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Publication number: 20150102398Abstract: Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.Type: ApplicationFiled: December 18, 2014Publication date: April 16, 2015Inventors: Henderikus Albert Van der Vegt, Guido Jozef Maria Dormans, Johan Dick Boter, Guoqiao Tao
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Patent number: 8278202Abstract: A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and then forming the control gate over the floating gate and the spacers.Type: GrantFiled: July 21, 2008Date of Patent: October 2, 2012Assignee: NXP B.V.Inventors: Antonius Maria Petrus Johannes Hendricks, Josephus Franciscus Antonius Maria Guelen, Guido Jozef Maria Dormans
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Publication number: 20120043600Abstract: Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.Type: ApplicationFiled: August 18, 2010Publication date: February 23, 2012Inventors: Henderikus Albert Van der Vegt, Guido Jozef Maria Dormans, Johan Dick Boter, Guoqiao Tao
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Publication number: 20110298034Abstract: A non-volatile memory cell (200) comprising a floating gate transistor (206) comprising a floating gate (10) positioned between a control gate (14) and a first channel region (232) and an access gate transistor (208) comprising an access gate (22) and a second channel region (234), the first channel region (232) comprising a first implant (242) with a first dosage level (234), and the second channel region comprising a second implant (244) having a second dosage level, the first dosage level being less than the second dosage level.Type: ApplicationFiled: June 2, 2011Publication date: December 8, 2011Applicant: NXP B.V.Inventors: Johan Dick Boter, Guoqiao Tao, Guido Jozef Maria Dormans, Joachim Christoph Hans Garbe
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Patent number: 8063429Abstract: A method for manufacturing on a substrate a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone in the substrate, thereafter forming the floating gate on the substrate, thereafter extending the floating gate using polysilicon spacers, and thereafter forming the control gate over the floating gate and the polysilicon spacers. Such a semiconductor device may be used in flash memory cells or EEPROMs.Type: GrantFiled: July 15, 2008Date of Patent: November 22, 2011Assignee: NXP B.V.Inventors: Antonius Maria Petrus Johannes Hendriks, Josephus Franciscus Antonius Maria Guelen, Guido Jozef Maria Dormans
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Publication number: 20090087976Abstract: A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and then forming the control gate over the floating gate and the spacers.Type: ApplicationFiled: July 21, 2008Publication date: April 2, 2009Inventors: Antonius Maria Petrus Hendriks, Josephus Franciscus Antoniu Guelen, Guido Jozef Maria Dormans
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Publication number: 20080283899Abstract: A method for manufacturing on a substrate (24) a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone (22) in the substrate (24), thereafter forming the floating gate (28) on the substrate (24), thereafter extending the floating gate (28) using polysilicon spacers (40), and thereafter forming the control gate (44) over the floating gate (28) and the polysilicon spacers (40). Such a semiconductor device may be used in flash memory cells or EEPROMs.Type: ApplicationFiled: July 15, 2008Publication date: November 20, 2008Applicant: NXP B.V.Inventors: ANTONIUS MARIA PETRUS JOHANNES HENDRIKS, JOSEPHUS FRANCISCUS ANTONIUS MARIA GUELEN, GUIDO JOZEF MARIA DORMANS
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Patent number: 7416939Abstract: A method for manufacturing on a substrate (24) a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone (22) in the substrate (24), thereafter forming the floating gate (28) on the substrate (24), thereafter extending the floating gate (28) using polysilicon spacers (40), and thereafter forming the control gate (44) over the floating gate (28) and the polysilicon spacers (40). Such a semiconductor device may be used in flash memory cells or EEPROMs.Type: GrantFiled: June 12, 2003Date of Patent: August 26, 2008Assignee: NXP B.V.Inventors: Antonius Maria Petrus Johannes Hendriks, Josephus Franciscus Antonius Maria Guelen, Guido Jozef Maria Dormans
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Patent number: 7148103Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE); manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE; providing a tile structure (25; 26); providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); and exposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.Type: GrantFiled: October 16, 2002Date of Patent: December 12, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Antonius Maria Petrus Johannes Hendriks, Guido Jozef Maria Dormans, Robertus Dominicus Joseph Verhaar
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Patent number: 7006381Abstract: The invention relates to a semiconductor device having a byte-erasable EEPROM memory comprising a matrix of rows and columns of memory cells. In order to provide a semiconductor device having a byte-erasable EEPROM which has a reduced chip size and increased density and which is suitable for low-power applications it is proposed according to the present invention that the memory cells each comprise a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, the selection transistor being further connected to a source line of the byte-erasable EEPROM memory, which source line is common for a plurality of memory cells, and the memory transistor being further connected to a bit line of the byte-erasable EEPROM memory, wherein the columns of memory cells are located in separate p-type wells separated by n-type wells.Type: GrantFiled: October 24, 2002Date of Patent: February 28, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Guido Jozef Maria Dormans, Robertus Dominicus Joseph Verhaar, Joachim Christoph Hans Garbe
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Publication number: 20040253827Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by:Type: ApplicationFiled: April 16, 2004Publication date: December 16, 2004Inventors: Antonius Maria Petrus Johannes Hendriks, Guido Jozef Maria Dormans, Robertus Dominicus Joseph Verhaar
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Patent number: 6815755Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25); the at least one memory cell having a floating gate (5), a tunnel oxide layer (11) between the floating gate and the substrate (1), a control gate (15), and a control oxide layer (13) between the control gate (15) and the floating gate (5); the at least one logic transistor (25) having a logic transistor gate (5′, 15″) and a logic transistor gate oxide (11″) between the logic transistor gate (5′, 15″) and the substrate (1), the tunnel oxide layer (11) of the memory cell (3) and the logic transistor gate oxide (11″) having a same or substantially same predetermined first thickness. The invention also relates to a method of manufacturing such a device and to such a device that also comprises a high voltage transistor (17) which is optionally made so as to be an integral part of at least the memory cell (3).Type: GrantFiled: March 18, 2003Date of Patent: November 9, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Roy Arthur Colclaser, Guido Jozef Maria Dormans, Donald Robert Wolters
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Publication number: 20030168694Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25);Type: ApplicationFiled: March 18, 2003Publication date: September 11, 2003Applicant: U.S. PHILIPS CORPORATIONInventors: Roy Arthur Colclaser, Guido Jozef Maria Dormans, Donald Robert Wolters
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Patent number: 6518619Abstract: A memory cell including: (a) a semiconductor substrate (1) provided with first and second diffusion layers (8); (b) a floating gate (11) on a floating gate insulating film (9); (c) a selection gate (4) on a selection gate insulating film (2); (d) a control gate (13) on a control gate insulating film (12); (e) the first and second diffusion layers (8) being arranged as the source and the drain of a field effect transistor structure, and the floating gate (11), selection gate (4) and control gate (13) being arranged as series field effect gates in the field effect transistor structure.Type: GrantFiled: December 19, 2000Date of Patent: February 11, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Robertus Dominicus Joseph Verhaar, Guido Jozef Maria Dormans
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Publication number: 20020182807Abstract: The invention relates to a semiconductor device comprising a semiconductor body (10) which is provided with an active semiconductor region (12) which borders on a surface (11) of said semiconductor body, which active semiconductor region is provided with a non-volatile memory cell comprising a source zone and a drain zone (29), a select gate (18), and a stacked gate structure (32) comprising a floating gate (26) and a control gate (25). The stacked gate extends above the select gate and covers a side wall (33) of said select gate, which side wall extends at least substantially perpendicularly to the surface of the semiconductor body. The stacked gate structure is insulated from the select gate by a layer of an insulating material (19, 35) that is applied to the select gate.Type: ApplicationFiled: April 18, 2002Publication date: December 5, 2002Inventor: Guido Jozef Maria Dormans
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Publication number: 20020130352Abstract: A semiconductor device comprising an EEPROM and a FLASH-EPROM memory is described. The EEPROM memory comprises a matrix of memory cells (ME) with a selection transistor (T2) having a selection gate (3) and arranged in series with a memory transistor (T1) having a floating gate (1) and a control gate (2). The selection transistor is also connected to a bit line (BL) and the memory transistor is also connected to a common source line (SO) of the EEPROM memory. The FLASH-EPROM memory comprises a matrix of memory cells (MF) with a memory transistor (T3) having a floating gate (4) and a control gate (5). The memory cells of the FLASH-EPROM memory also comprise a transistor (T4) having a control gate (6) connected in series with the memory cell. The memory transistor is also connected to a bit line, and the transistor, which is connected in series with the memory transistor, is also connected to a common source line (SO) of the FLASH-EPROM memory.Type: ApplicationFiled: December 13, 2001Publication date: September 19, 2002Inventors: Guido Jozef Maria Dormans, Johannes Dijkstra, Robertus Dominicus Joseph Verhaar
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Publication number: 20010030341Abstract: A memory cell including:Type: ApplicationFiled: December 19, 2000Publication date: October 18, 2001Inventors: Robertus Dominicus Joseph Verhaar, Guido Jozef Maria Dormans
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Publication number: 20010004120Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25);Type: ApplicationFiled: December 21, 2000Publication date: June 21, 2001Inventors: Roy Arthur Colclaser, Guido Jozef Maria Dormans, Donald Robert Wolters