Abstract: A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.

Abstract: A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

Abstract: Provided is a memory. The memory includes: a plurality of memory cells, word lines, and bit lines; wherein each of the memory cells comprises: a first transistor, wherein a first source of the first transistor is electrically connected to the bit line; a second transistor, connected in series to the first transistor; and a capacitor, electrically connected to a second drain of the second transistor. The first transistor and the second transistor are both n-type transistors or p-type transistors, and a first gate of the first transistor and a second gate of the second transistor are electrically connected to the word line.

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

Abstract: A 3D stacked semiconductor device, a manufacturing method therefor, and an electronic equipment are disclosed. The 3D stacked semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a base substrate; a word line penetrating through the transistors of the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; wherein each transistor includes a semiconductor layer surrounding a side wall of the word line, a gate insulation layer disposed between the side wall of the word line and the semiconductor layer, a plurality of semiconductor layers of the plurality of transistors are disposed at intervals in a direction in which the word line extends; each of the protective layers respectively surrounds and covers an outer side wall of a corresponding semiconductor layer, and two adjacent protective layers are disconnected from each other.

Abstract: A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.

Abstract: The semiconductor device includes: a substrate; a plurality of memory cell columns, wherein each memory cell column includes a plurality of memory cells, arranged and stacked on one side of the substrate in a first direction, and the plurality of memory cell columns are arranged on the substrate in a second direction and in a third direction to form an array; the memory cells each include a transistor and a capacitor, the transistor including a semiconductor layer and a gate, and semiconductor layer includes a source region, an inversion channel region and a drain region; a plurality of bit lines, extending in the first direction, wherein the source regions of the transistors of the plurality of memory cells in two adjacent memory cell columns in the second direction, are all connected to one bit line; and a plurality of word lines, extending in the third direction.

Abstract: Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.

Abstract: A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data.

Abstract: A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.

Abstract: A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data.

Abstract: A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.

Abstract: A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.

Abstract: A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer thereon in the gate trench; forming a first tungsten (W) layer on a surface of the metal gate layer, and forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions; and filling with W through an atomic layer deposition (ALD) process. The blocking layer prevents ions in the precursors from aggregating on an interface and penetrating into the metal gate layer and the gate dielectric layer. At the same time, adhesion of W is enhanced, a process window of W during planarization is increased, reliability of the device is improved and the gate resistance is further reduced.

Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

Abstract: Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.

Abstract: A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.