Patents by Inventor Guillaume Bouche

Guillaume Bouche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11749715
    Abstract: Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Guillaume Bouche, Sean T. Ma, Andy Chih-Hung Wei
  • Publication number: 20230197717
    Abstract: Gate-all-around structures having neighboring fin-based devices are described. In an example, an integrated circuit structure includes a first device including a fin above a substrate, and a first gate structure over the fin. The integrated circuit structure also includes a second device including a vertical arrangement of horizontal nanowires above a sub-fin structure above the substrate, and a second gate structure surrounding the vertical arrangement of horizontal nanowires.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Guillaume BOUCHE, Andy Chih-Hung WEI
  • Publication number: 20230197713
    Abstract: Gate-all-around integrated circuit structures having raised wall structures for epitaxial source or drain region confinement are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface above a top surface of the first and second vertical arrangements of nanowires.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Guillaume BOUCHE, Andy Chih-Hung WEI, Anand S. MURTHY, Aryan NAVABI-SHIRAZI, Mohammad HASAN
  • Publication number: 20230197714
    Abstract: Gate-all-around integrated circuit structures having backside contact self-aligned to epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Inventors: Guillaume BOUCHE, Aryan NAVABI-SHIRAZI, Andy Chih-Hung WEI, Mauro J. KOBRINSKY, Shaun MILLS, Pratik PATEL
  • Publication number: 20230197819
    Abstract: Integrated circuit structures having a metal gate plug landed on a dielectric dummy fin, and methods of fabricating integrated circuit structures having a metal gate plug landed on a dielectric dummy fin, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric dummy fin is laterally spaced apart from the plurality of horizontally stacked nanowires, the dielectric dummy fin having a bottommost surface below an uppermost surface of the sub-fin. A dielectric gate plug is on the dielectric dummy fin.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Guillaume BOUCHE, Andy Chih-Hung WEI
  • Publication number: 20230073304
    Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first dielectric material continuously around the first gate metal; and a second dielectric material continuously around the second gate metal, wherein the first dielectric material and the second dielectric material are present between the first gate metal and the second gate metal.
    Type: Application
    Filed: September 19, 2022
    Publication date: March 9, 2023
    Applicant: Intel Corporation
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Sean T. Ma
  • Publication number: 20230057326
    Abstract: Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate layer between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Applicant: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Anand S. Murthy, Yang-Chun Cheng, Ryan Pearce, Guillaume Bouche
  • Publication number: 20230052975
    Abstract: Techniques are provided to form semiconductor devices having a multi-layer spacer structure. In an example, a semiconductor device includes a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor region. A spacer structure made up of one or more dielectric layers is present along a sidewall of the gate structure and along a sidewall of the source region or the drain region. The spacer structure has three different portions: a first portion along the sidewall of the gate, a second portion along the sidewall of the source or drain region, and a third portion that connects between the first two portions. The third portion of the spacer structure has a multi-layer configuration while the first and second portions have a fewer number of material layers.
    Type: Application
    Filed: August 16, 2021
    Publication date: February 16, 2023
    Applicant: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Guillaume Bouche
  • Publication number: 20230032866
    Abstract: Techniques to form self-aligned lateral contacts. In an example, a first trench contact contacts a source or drain region of a transistor. A second trench contact includes non-contiguous first and second portions, each portion having a top surface that is co-planar with a top surface of the first trench contact as well as a top surface of the gate structure. A sidewall of the second trench contact is self-aligned to, and interfaces with, a sidewall of the first trench contact. A via extends from the first portion of the second trench contact to an underlying power rail. In some cases, the second portion of the second trench contact extends over a source or drain region of another transistor, without contacting that source or drain region. The fly-over portion of the second trench contact has a maximum height that is shorter than a maximum height of the first trench contact.
    Type: Application
    Filed: July 27, 2021
    Publication date: February 2, 2023
    Applicant: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Yang-Chun Cheng, Shaestagir Chowdhury, Guillaume Bouche
  • Publication number: 20220416057
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to manufacturing a gate structure that includes adjacent gates that are coupled with the first fin and a second fin, with a metal gate cut across the adjacent gates and a trench connector between the adjacent gates that electrically couples the first fin and the second fin. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Guillaume BOUCHE, Shashi VYAS, Andy Chih-Hung WEI, Leonard P. GULER
  • Publication number: 20220415736
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to protecting metal gates within transistor gate structures during SAC patterning. In particular, embodiments include area selective deposition techniques to deposit films on the gate or on a gate cap that have a good selectivity to SAC etch. In embodiments the film may include a combination of zirconium and/or oxygen, or may include zirconium oxide. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Guillaume BOUCHE, Shashi VYAS, Andy Chih-Hung WEI, Charles H. WALLACE, Sachin PANDIJA
  • Publication number: 20220415796
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a transistor structure that includes a buried power rail (BPR) located within the transistor structure at a level below a height of one or more of the fins of the transistor structure. The BPR may be located proximate to a bottom substrate of the transistor structure. In embodiments, the transistor structure includes a protective layer, which can include one or more dielectric layers, above the BPR to protect the BPR during stages of transistor structure manufacture. In embodiments, portions of the protective layer may also be used to constrain epitaxial growth during stages of manufacturing of the transistor structure. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Andy Chih-Hung WEI, Guillaume BOUCHE
  • Publication number: 20220359658
    Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Applicant: Intel Corporation
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Sean T. Ma
  • Publication number: 20220344459
    Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 27, 2022
    Applicant: Intel Corporation
    Inventors: Sean T. Ma, Andy Chih-Hung Wei, Guillaume Bouche
  • Patent number: 11482524
    Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first dielectric material continuously around the first gate metal; and a second dielectric material continuously around the second gate metal, wherein the first dielectric material and the second dielectric material are present between the first gate metal and the second gate metal.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Sean T. Ma
  • Patent number: 11450736
    Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Andy Chih-Hung Wei, Guillaume Bouche
  • Publication number: 20220293517
    Abstract: Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using selective growth, e.g., assisted by a self-assembled monolayer (SAM) material.
    Type: Application
    Filed: March 10, 2021
    Publication date: September 15, 2022
    Applicant: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Guillaume Bouche
  • Publication number: 20220293516
    Abstract: Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using subtractive patterning, while the top via portion may be formed using a different fabrication technique, such as Damascene fabrication.
    Type: Application
    Filed: March 10, 2021
    Publication date: September 15, 2022
    Applicant: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Guillaume Bouche
  • Patent number: 11430866
    Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Sean T. Ma
  • Publication number: 20220231121
    Abstract: Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Applicant: Intel Corporation
    Inventors: Guillaume Bouche, Sean T. Ma, Andy Chih-Hung Wei