Patents by Inventor Guillaume Bouche

Guillaume Bouche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210296506
    Abstract: Described herein are IC devices with non-planar SiGe transistors fabricated using silicon replacement. Silicon replacement as described herein refers to providing, over a support structure (e.g., a substrate, a wafer, a chip, or a die), a channel body for a non-planar transistor, where the channel body includes silicon, providing a cladding layer that includes germanium over at least a portion of the channel body, and annealing the channel body so that at least some of the germanium diffuses into the channel body. The channel body is a fin if the transistor is a FinFET transistor, and is a nanoribbon or a nanowire if the transistor is a nanoribbon-based transistor. Fabricating non-planar SiGe transistors using silicon replacement advantageously allows forming IC devices with both silicon and SiGe transistors on a single support structure.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 23, 2021
    Applicant: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Jack T. Kavalieros, Guillaume Bouche
  • Patent number: 11127627
    Abstract: A method for forming an interconnection structure for a semiconductor device is provided.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: September 21, 2021
    Assignee: IMEC VZW
    Inventors: Frederic Lazzarino, Guillaume Bouche, Juergen Boemmels
  • Patent number: 11061315
    Abstract: Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: July 13, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Jia Zeng, Guillaume Bouche, Lei Sun, Geng Han
  • Patent number: 10833161
    Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second se
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 10, 2020
    Assignees: IMEC VZW, GLOBALFOUNDRIES INC.
    Inventors: Syed Muhammad Yasser Sherazi, Julien Ryckaert, Juergen Boemmels, Guillaume Bouche
  • Publication number: 20200286998
    Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Patent number: 10770388
    Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Veeraraghavan S. Basker, Kangguo Cheng, Jia Zeng, Youngtag Woo, Mahender Kumar, Guillaume Bouche
  • Patent number: 10700170
    Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Publication number: 20200194306
    Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Ruilong Xie, Hui Zang, Lei Sun, Lars Liebmann, Daniel Chanemougame, Guillaume Bouche
  • Patent number: 10685874
    Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Hui Zang, Lei Sun, Lars Liebmann, Daniel Chanemougame, Guillaume Bouche
  • Publication number: 20200168500
    Abstract: A method for forming an interconnection structure for a semiconductor device is provided.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 28, 2020
    Inventors: Frederic Lazzarino, Guillaume Bouche, Juergen Boemmels
  • Publication number: 20200159105
    Abstract: Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jia Zeng, Guillaume Bouche, Lei Sun, Geng Han
  • Patent number: 10644136
    Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Patent number: 10586762
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interrupted small block shape structures (e.g., cut metal lines forming cell boundaries) and methods of manufacture. The structure includes: a plurality of wiring lines with cuts that form a cell boundary; and at least one wiring line extending beyond the cell boundary and which is continuous from cell to cell.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Lars W. Liebmann
  • Patent number: 10566248
    Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Ruilong Xie, Chanro Park, Guillaume Bouche
  • Patent number: 10559503
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
  • Publication number: 20200035567
    Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Inventors: Daniel Chanemougame, Ruilong Xie, Chanro Park, Guillaume Bouche
  • Publication number: 20200006112
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Nicholas V. LICAUSI, Guillaume BOUCHE, Lars W. LIEBMANN
  • Publication number: 20190385946
    Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Applicant: International Business Machines Corporation
    Inventors: Ruilong Xie, Veeraraghavan S. Basker, Kangguo Cheng, Jia Zeng, Youngtag Woo, Mahender Kumar, Guillaume Bouche
  • Patent number: 10475692
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas V. Licausi, Guillaume Bouche, Lars W. Liebmann
  • Patent number: 10460067
    Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 29, 2019
    Assignees: IMEC vzw, Globalfoundries Inc.
    Inventors: Syed Muhammad Yasser Sherazi, Guillaume Bouche, Julien Ryckaert