Abstract: Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using subtractive patterning, while the top via portion may be formed using a different fabrication technique, such as Damascene fabrication.

Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.

Abstract: Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.

Abstract: Gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires include silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure.

Abstract: Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Abstract: Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.

Abstract: Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact.

Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.

Abstract: Methods for fabricating an IC structure by applying self-assembled monolayers (SAMs) are disclosed. An example IC structure includes a stack of three metallization layers provided over a support structure, where the first metallization layer includes a bottom metal line, the third metallization layer includes a top metal line, and the second metallization layer includes a via coupled between the bottom metal line and the top metal line, where via's sidewalls are enclosed by a first dielectric material. Application of one or more SAMs results in at least a portion of the via's sidewalls being lined with a second dielectric material so that the second dielectric material is between the first dielectric material and an electrically conductive material of the via, where the dielectric constant of the second dielectric material is higher than that of the first dielectric material and lower than about 6.

Abstract: Methods for fabricating interconnect arrangements of a metallization layer Mx by using stitching that is enabled by subtractive metallization are disclosed. An example method includes providing a metal layer and a collection layer over the metal layer. The method then includes forming openings for two sets of metal lines by performing a first lithographic process to provide, in the collection layer, first openings for a first set of lines, and then performing a second lithographic process to provide, in the collection layer, second openings for a second set of lines. The method further includes performing a third lithographic process to provide a further opening (a stitch opening) that overlaps with at least one of the first openings of a first track and at least one of the second openings of a second track, and, finally, transferring the pattern of the first, second, and stitch openings to the metal layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

Abstract: Disclosed herein are non-planar transistor (e.g., nanoribbon) arrangements having asymmetric gate enclosures on at least one side. An example transistor arrangement includes a channel material shaped as a nanoribbon, and a gate stack wrapping around at least a portion of a first face of the nanoribbon, a sidewall, and a portion of a second face of the nanoribbon. Portions of the gate stack provided over the first and second faces of the nanoribbon extend in a direction parallel to the longitudinal axis of the nanoribbon for a certain distance that may be referred to as a “gate length.” A portion of the gate stack wrapping around the sidewall of the nanoribbon does not extend along the entire gate length, but, rather, extends over less than a half of the gate length, e.g., about one third of the gate length, thus making the gate enclosure on that sidewall asymmetric.

Abstract: Disclosed herein are methods for manufacturing an integrated circuit (IC) structure, e.g., for manufacturing a metallization stack portion of an IC structure, with one or more self-aligned vias integrated in the back end of line (BEOL), and related semiconductor devices. The methods may employ direct metal etch for scaling the BEOL pitches of the metallization layers. In one aspect, an example method results in fabrication of a via that is self-aligned to both a metal line above it and a metal line below it. Methods described herein may provide improvements in terms of one or more of reducing the misalignment between vias and electrically conductive structures connected thereto, reducing the RC delays, and increasing reliability if the final IC structures.

Abstract: Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.

Abstract: Discussed herein are device contacts in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact; a gate contact, wherein the gate contact is in contact with a gate and with the first S/D contact; and a second S/D contact, wherein a height of the second S/D contact is less than a height of the first S/D contact.

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first dielectric material continuously around the first gate metal; and a second dielectric material continuously around the second gate metal, wherein the first dielectric material and the second dielectric material are present between the first gate metal and the second gate metal.

Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.

Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.