Patents by Inventor Guk Cheon Kim
Guk Cheon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10203380Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.Type: GrantFiled: December 14, 2017Date of Patent: February 12, 2019Assignees: SK Hynix Inc., Toshiba Memory CorporationInventors: Ku-Youl Jung, Guk-Cheon Kim, Toshihiko Nagase, Daisuke Watanabe, Won-Joon Choi, Youngmin Eeh, Kazuya Sawada
-
Patent number: 10170691Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.Type: GrantFiled: June 20, 2016Date of Patent: January 1, 2019Assignees: SK Hynix Inc., TOSHIBA MEMORY CORPORATIONInventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine
-
Patent number: 10153423Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.Type: GrantFiled: December 15, 2017Date of Patent: December 11, 2018Assignees: SK Hynix Inc., Toshiba Memory CorporationInventors: Yang-Kon Kim, Guk-Cheon Kim, Jae-Hyoung Lee, Jong-Koo Lim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh
-
Patent number: 10133689Abstract: This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.Type: GrantFiled: March 25, 2016Date of Patent: November 20, 2018Assignee: SK hynix Inc.Inventors: Guk-Cheon Kim, Yang-Kon Kim, Seung Mo Noh, Won-Joon Choi
-
Patent number: 10134458Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.Type: GrantFiled: January 8, 2018Date of Patent: November 20, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim
-
Patent number: 10120799Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.Type: GrantFiled: August 11, 2017Date of Patent: November 6, 2018Assignee: SK hynix Inc.Inventors: Cha-Deok Dong, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim
-
Patent number: 10103318Abstract: According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of Co and Fe, and a material having a higher standard electrode potential than Co and Fe.Type: GrantFiled: September 12, 2016Date of Patent: October 16, 2018Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX, INC.Inventors: Daisuke Watanabe, Yang Kon Kim, Makoto Nagamine, Youngmin Eeh, Koji Ueda, Toshihiko Nagase, Kazuya Sawada, Guk Cheon Kim, Bo Mi Lee, Won Joon Choi
-
Publication number: 20180284199Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.Type: ApplicationFiled: December 14, 2017Publication date: October 4, 2018Inventors: Ku-Youl JUNG, Guk-Cheon KIM, Toshihiko NAGASE, Daisuke WATANABE, Won-Joon CHOI, Youngmin EEH, Kazuya SAWADA
-
Patent number: 10062424Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.Type: GrantFiled: July 17, 2017Date of Patent: August 28, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi
-
Publication number: 20180240973Abstract: A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a Magnetic Tunnel Junction (MTJ) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.Type: ApplicationFiled: February 2, 2018Publication date: August 23, 2018Inventors: Ku-Youl Jung, Guk-Cheon Kim, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
-
Publication number: 20180233187Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer including a CoFeBAl alloy and having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the CoFeBAl alloy may have an Al content less than 10 at %.Type: ApplicationFiled: January 22, 2018Publication date: August 16, 2018Inventors: Jong-Koo Lim, Yang-Kon Kim, Ku-Youl Jung, Guk-Cheon Kim, Jeong-Myeong Kim
-
Patent number: 10042559Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.Type: GrantFiled: January 30, 2017Date of Patent: August 7, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Guk-Cheon Kim, Ku-Youl Jung, Jong-Koo Lim, Won-Joon Choi
-
Publication number: 20180211994Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory may include an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer formed under the MTJ structure, wherein the under layer may include metals and oxides of the metals.Type: ApplicationFiled: November 2, 2017Publication date: July 26, 2018Inventors: Guk-Cheon Kim, Ku-Youl Jung, Yang-Kon Kim, Jae-Hyoung Lee, Jong-Koo Lim
-
Publication number: 20180198060Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.Type: ApplicationFiled: December 15, 2017Publication date: July 12, 2018Inventors: Yang-Kon KIM, Guk-Cheon KIM, Jae-Hyoung LEE, Jong-Koo LIM, Ku-Youl JUNG, Toshihiko NAGASE, Youngmin EEH
-
Patent number: 10002903Abstract: Implementations of the disclosed technology provide an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a magnetic tunnel junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer sandwiched between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer includes a first under layer including a silicon-based alloy, and a second under layer located on the first under layer and including a metal.Type: GrantFiled: March 18, 2016Date of Patent: June 19, 2018Assignee: SK hynix Inc.Inventors: Jong-Koo Lim, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Won-Joon Choi
-
Patent number: 9991313Abstract: According to one embodiment, a magnetic memory includes a first magnetic layer, a second magnetic layer, a non-magnetic intermediate layer provided between the first magnetic layer and the second magnetic layer and an underlying layer provided on an opposite side of the first magnetic layer with respect to the intermediate layer, and the underlying layer contains AlN of a hcp structure.Type: GrantFiled: March 12, 2015Date of Patent: June 5, 2018Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX, INC.Inventors: Daisuke Watanabe, Makoto Nagamine, Youngmin Eeh, Koji Ueda, Toshihiko Nagase, Kazuya Sawada, Yang Kon Kim, Bo Mi Lee, Guk Cheon Kim, Won Joon Choi, Ki Seon Park
-
Publication number: 20180130512Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.Type: ApplicationFiled: January 8, 2018Publication date: May 10, 2018Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim
-
Publication number: 20180130945Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: ApplicationFiled: January 8, 2018Publication date: May 10, 2018Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
-
Patent number: 9865806Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: GrantFiled: November 17, 2016Date of Patent: January 9, 2018Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
-
Patent number: 9865319Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.Type: GrantFiled: September 6, 2015Date of Patent: January 9, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim