Patents by Inventor Guk Cheon Kim
Guk Cheon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9841915Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure comprising a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer may include: a first under layer including a silicon-based alloy; a second under layer including a metal; and a blocking layer interposed between the first under layer and the second under layer and including an amorphous material.Type: GrantFiled: April 21, 2017Date of Patent: December 12, 2017Assignee: SK hynix Inc.Inventors: Jong-Koo Lim, Guk-Cheon Kim, Yang-Kon Kim, Seung-Mo Noh, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20170344476Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.Type: ApplicationFiled: August 11, 2017Publication date: November 30, 2017Inventors: Cha-Deok Dong, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim
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Publication number: 20170329518Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.Type: ApplicationFiled: January 30, 2017Publication date: November 16, 2017Inventors: Yang-Kon Kim, Guk-Cheon Kim, Ku-Youl Jung, Jong-Koo Lim, Won-Joon Choi
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Publication number: 20170316814Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20170263680Abstract: According to one embodiment, a magnetoresistive memory device includes an electrode, a first layer which is provided on the electrode and includes an amorphous portion in at least a part of an electrode side, and a magnetoresisive element provided on the first layer.Type: ApplicationFiled: September 16, 2016Publication date: September 14, 2017Applicants: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.Inventors: Kenichi YOSHINO, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Makoto NAGAMINE, Won Joon CHOI, Guk Cheon KIM, Yang Kon KIM, Jong Koo LIM
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Patent number: 9734060Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.Type: GrantFiled: July 1, 2015Date of Patent: August 15, 2017Assignee: SK hynix Inc.Inventors: Cha-Deok Dong, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim
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Publication number: 20170222133Abstract: Provided are electronic device including a variable resistance element and a method for fabricating an electronic device including a variable resistance element. The electronic device including a variable resistance element includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include cooling the substrate, before forming the magnetic correction layer such that the magnetic correction layer is formed over the cooled substrate.Type: ApplicationFiled: June 20, 2016Publication date: August 3, 2017Inventors: Jong-Koo LIM, Won-Joon CHOI, Guk-Cheon KIM, Yang-Kon KIM, Ku-Youl JUNG, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Makoto NAGAMINE
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Patent number: 9722172Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a hole; a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein an upper portion of the conductive pattern includes a first amorphous region.Type: GrantFiled: July 1, 2015Date of Patent: August 1, 2017Assignee: SK hynix Inc.Inventors: Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim
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Patent number: 9711202Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.Type: GrantFiled: March 17, 2016Date of Patent: July 18, 2017Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20170200487Abstract: Disclosed are an electronic device comprising a semiconductor memory. The semiconductor memory includes a variable resistance element including a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first free layer adjacent to the tunnel barrier layer and having a perpendicular magnetic anisotropy at an interface with the tunnel barrier layer; and a second free layer spaced apart from the tunnel barrier layer by the first free layer and having a saturation magnetization lower than a saturation magnetization of the first free layer.Type: ApplicationFiled: March 24, 2017Publication date: July 13, 2017Inventors: Guk-Cheon Kim, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Yang-Kon Kim
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Publication number: 20170154662Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.Type: ApplicationFiled: March 17, 2016Publication date: June 1, 2017Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20170084667Abstract: Implementations of the disclosed technology provide an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a magnetic tunnel junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer sandwiched between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer includes a first under layer including a silicon-based alloy, and a second under layer located on the first under layer and including a metal.Type: ApplicationFiled: March 18, 2016Publication date: March 23, 2017Inventors: Jong-Koo Lim, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20170069837Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: ApplicationFiled: November 17, 2016Publication date: March 9, 2017Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
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Publication number: 20170062712Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.Type: ApplicationFiled: November 16, 2016Publication date: March 2, 2017Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
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Publication number: 20170024336Abstract: This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.Type: ApplicationFiled: March 25, 2016Publication date: January 26, 2017Inventors: Guk-Cheon Kim, Yang-Kon Kim, Seung Mo Noh, Won-Joon Choi
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Publication number: 20160380182Abstract: According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of Co and Fe, and a material having a higher standard electrode potential than Co and Fe.Type: ApplicationFiled: September 12, 2016Publication date: December 29, 2016Applicants: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.Inventors: Daisuke WATANABE, Yang Kon KIM, Makoto NAGAMINE, Youngmin EEH, Koji UEDA, Toshihiko NAGASE, Kazuya SAWADA, Guk Cheon KIM, Bo Mi LEE, Won Joon CHOI
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Patent number: 9529714Abstract: An electronic device includes a semiconductor memory, and the semiconductor memory includes a first magnetic layer having a variable magnetization direction; a second magnetic layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a ferromagnetic material with molybdenum (Mo) added thereto.Type: GrantFiled: December 3, 2014Date of Patent: December 27, 2016Assignees: SK Hynix Inc., Kabushiki Kaisha ToshibaInventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Daisuke Watanabe, Makoto Nagamine, Young-Min Eeh, Koji Ueda, Toshihiko Nagase, Kazuya Sawada
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Patent number: 9520550Abstract: An electronic device is provided to include a semiconductor memory including a variable resistance element. The variable resistance element may include a variable resistance pattern including a first electrode layer, a variable resistance layer, and a second electrode layer that are sequentially stacked; and a switching assist structure spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and including multilayered conductive structures that are vertically spaced from one another.Type: GrantFiled: September 11, 2015Date of Patent: December 13, 2016Assignee: SK hynix Inc.Inventors: Chi-Ho Kim, Sung-Joon Yoon, Guk-Cheon Kim, Seung-Mo Noh
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Patent number: 9502639Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a seed layer including conductive hafnium silicate; a first magnetic layer formed over the seed layer; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer.Type: GrantFiled: January 17, 2014Date of Patent: November 22, 2016Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh
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Publication number: 20160308113Abstract: An electronic device is provided to include a semiconductor memory including a variable resistance element. The variable resistance element may include a variable resistance pattern including a first electrode layer, a variable resistance layer, and a second electrode layer that are sequentially stacked; and a switching assist structure spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and including multilayered conductive structures that are vertically spaced from one another.Type: ApplicationFiled: September 11, 2015Publication date: October 20, 2016Inventors: Chi-Ho Kim, Sung-Joon Yoon, Guk-Cheon Kim, Seung-Mo Noh