Abstract: Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A suicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

Abstract: Provided is a semiconductor device having an etch-resistant L-shaped spacer and a fabrication method thereof. The semiconductor device comprises a semiconductor substrate, a gate insulating layer formed on the semiconductor substrate, a gate electrode formed on the gate insulating layer, an L-shaped lower spacer conformally formed on sidewalls of the gate electrode and a portion of the substrate, an etch-resistant L-shaped spacer conformally formed on the L-shaped lower spacer, low-concentration source/drain regions aligned to sides of sidewall portions of the L-shaped lower spacer and formed within the substrate, and high-concentration source/drain regions aligned to sides of a bottom portions of the etch-resistant L-shaped spacer and formed within the substrate.

Abstract: MOSFETs with pocket regions are fabricated. A gate electrode layer is formed on a semiconductor substrate; and lightly doped drain regions are formed in the semiconductor substrate adjacent the gate electrode layer. A blocking pattern is formed on the semiconductor substrate where the gate electrode layer is formed. The blocking pattern is adjacent and spaced apart from the gate electrode layer a predetermined distance and exposes portions of the semiconductor substrate adjacent sidewalls of the gate electrode layer. Pocket regions are formed in the semiconductor substrate by implanting impurity ions using the gate electrode layer and the blocking pattern as an ion implantation mask.

Abstract: A cap with sunglasses has an elongated holder mounted on the underside of the visor. A carrier partially surrounds the holder and is slidable therealong for adjusting the position of sunglasses mounted on the carrier. A latching assembly is captured in the carrier and has projections in the form of tines for being selectively inserted between teeth disposed along the length of the holder. A spring normally urges the latching means to insert the tines between the holder teeth. Movement of the carrier relative to the holder is permitted when the latching assembly is pressed against the restoring spring force to disengage the projections on the latching assembly from between the holder teeth to permit adjustment of the position of the sunglasses.

Abstract: In a method of forming a CMOS device, first and second conductive structures are formed on a substrate. An insulation layer is formed on the substrate having the first and second conductive structures. The insulation layer is patterned to form an insulation layer pattern having a first portion on the first conductive structure and a second portion on the second conductive structure. The first portion has a compressive stress and functions as an etch stop layer. The second portion functions as an etch stop layer.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract: A cap with sunglasses has an elongated holder mounted on the underside of the visor. A carrier partially surrounds the holder and is slidable therealong for adjusting the position of sunglasses mounted on the carrier. A latching assembly is captured in the carrier and has projections in the form of tines for being selectively inserted between teeth disposed along the length of the holder. A spring normally urges the latching means to insert the tines between the holder teeth. Movement of the carrier relative to the holder is permitted when the latching assembly is pressed against the restoring spring force to disengage the projections on the latching assembly from between the holder teeth to permit adjustment of the position of the sunglasses.

Abstract: A method of fabricating a semiconductor device having an L-shaped spacer comprises forming a gate pattern on a transistor region of a semiconductor substrate. A disposable spacer is formed on an insulating layer of sidewalls of the gate pattern. Deeply doped source/drain regions are formed aligned with the disposable spacer of the transistor region and in the semiconductor substrate of a resistor region. The disposable spacer and the first insulating layer are removed. A shallowly doped source/drain region is formed aligned with the sides of the gate pattern and adjacent to the deeply doped source/drain region of the transistor region. An L-shaped spacer is formed adjacent to the sidewalls of the gate pattern of the transistor region. A suicide formation protecting layer pattern is simultaneously formed on the resistor region. A metal silicide is formed on an upper surface of the gate electrode, the deeply doped source/drain regions.

Abstract: Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A suicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

Abstract: A semiconductor device includes: a silicon substrate; a source/drain region formed in the substrate including a lightly doped region and an adjacent heavily doped region, the depth of the heavily doped region being greater than the depth of the lightly doped region; a gate oxide layer on the silicon substrate; and a notched gate electrode on the substrate, the notched gate electrode including a notch along an outer side surface of a lower portion such that a top portion of the notched gate electrode is wider than the lower portion, the gate oxide layer extending between the interface of the notched gate electrode and the substrate, and a gate poly oxide layer provided along an outer side surface of the notched gate electrode and along an inner wall of the notch, a portion of the lightly doped region being under the notch.

Abstract: The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer.

Abstract: MOSFETs with pocket regions are fabricated. A gate electrode layer is formed on a semiconductor substrate; and lightly doped drain regions are formed in the semiconductor substrate adjacent the gate electrode layer. A blocking pattern is formed on the semiconductor substrate where the gate electrode layer is formed. The blocking pattern is adjacent and spaced apart from the gate electrode layer a predetermined distance and exposes portions of the semiconductor substrate adjacent sidewalls of the gate electrode layer. Pocket regions are formed in the semiconductor substrate by implanting impurity ions using the gate electrode layer and the blocking pattern as an ion implantation mask.

Abstract: An integrated circuit device is formed by forming a gate conductive layer on a gate insulating layer on a substrate. The gate conductive layer and the gate insulating layer are dry-etched to provide a gate structure. A buffer layer is formed on the sidewall of the gate structure covering an interface in the gate structure between the gate conductive layer and the gate insulating layer. The gate structure is annealed, through the buffer layer, to repair damage caused during the dry-etching.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Abstract: A method of fabricating a semiconductor device having an L-shaped spacer is provided. A buffer dielectric layer, a first dielectric layer, and a second dielectric layer are sequentially formed on the surface of the gate electrode and on the semiconductor substrate. Next, the second dielectric layer is etched to form a first disposable spacer on the first dielectric layer at both sidewalls of the gate electrode. Next, a deeply doped source and drain region is formed on the semiconductor substrate to be aligned to the first disposable spacer. Next, the first disposable spacer and the first dielectric layer are sequentially removed. Next, a shallowly doped source and drain region is formed on the semiconductor substrate at both sidewalls of the gate electrode adjacent to the deeply doped source and drain region. Next, a third dielectric layer, a fourth dielectric layer, and a fifth dielectric layer are sequentially formed on the buffer dielectric layer.

Abstract: The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer.

Abstract: A method of fabricating a semiconductor device having an L-shaped spacer comprises forming a gate pattern on a transistor region of a semiconductor substrate. A disposable spacer is formed on an insulating layer of sidewalls of the gate pattern. Deeply doped source/drain regions are formed aligned with the disposable spacer of the transistor region and in the semiconductor substrate of a resistor region. The disposable spacer and the first insulating layer are removed. A shallowly doped source/drain region is formed aligned with the sides of the gate pattern and adjacent to the deeply doped source/drain region of the transistor region. An L-shaped spacer is formed adjacent to the sidewalls of the gate pattern of the transistor region. A silicide formation protecting layer pattern is simultaneously formed on the resistor region. A metal silicide is formed on an upper surface of the gate electrode, the deeply doped source/drain regions.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.