Patents by Inventor Gun KO

Gun KO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6693325
    Abstract: The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: February 17, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Gun Ko, Byung-Sun Kim
  • Patent number: 6693013
    Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: February 17, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Geum-Jong Bae, Nae-In Lee, Hwa-Sung Rhee, Young-Gun Ko, Tae-Hee Choe, Sang-Su Kim
  • Patent number: 6689648
    Abstract: The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: February 10, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Gun Ko, Byung-Sun Kim, Young-Wug Kim
  • Publication number: 20030143785
    Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 31, 2003
    Inventors: Young-Wug Kim, Byung-Sun Kim, Hee-Sung Kang, Young-Gun Ko, Sung-Bae Park, Min-Su Kim, Kwang-Il Kim
  • Publication number: 20030057455
    Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.
    Type: Application
    Filed: November 1, 2002
    Publication date: March 27, 2003
    Inventors: Young-Wug Kim, Byung-Sun Kim, Hee-Sung Kang, Young-Gun Ko, Sung-Bae Park
  • Patent number: 6521959
    Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: February 18, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Wug Kim, Byung-Sun Kim, Hee-Sung Kang, Young-Gun Ko, Sung-Dae Park, Min-Su Kim, Kwang-Il Kim
  • Publication number: 20030027414
    Abstract: A method of fabricating a semiconductor device having an L-shaped spacer is provided. A buffer dielectric layer, a first dielectric layer, and a second dielectric layer are sequentially formed on the surface of the gate electrode and on the semiconductor substrate. Next, the second dielectric layer is etched to form a first disposable spacer on the first dielectric layer at both sidewalls of the gate electrode. Next, a deeply doped source and drain region is formed on the semiconductor substrate to be aligned to the first disposable spacer. Next, the first disposable spacer and the first dielectric layer are sequentially removed. Next, a shallowly doped source and drain region is formed on the semiconductor substrate at both sidewalls of the gate electrode adjacent to the deeply doped source and drain region. Next, a third dielectric layer, a fourth dielectric layer, and a fifth dielectric layer are sequentially formed on the buffer dielectric layer.
    Type: Application
    Filed: March 25, 2002
    Publication date: February 6, 2003
    Inventor: Young-gun Ko
  • Patent number: 6498370
    Abstract: A silicon-on-insulator (SOD integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: December 24, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Wug Kim, Byung-Sun Kim, Hee-Sung Kang, Young-Gun Ko, Sung-Bae Park
  • Publication number: 20020182795
    Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.
    Type: Application
    Filed: March 25, 2002
    Publication date: December 5, 2002
    Inventors: Geum-Jong Bae, Nae-In Lee, Hwa-Sung Rhee, Young-Gun Ko, Tae-Hee Choe, Sang-Su Kim
  • Publication number: 20020142523
    Abstract: A semiconductor device includes: a silicon substrate; a source/drain region formed in the substrate including a lightly doped region and an adjacent heavily doped region, the depth of the heavily doped region being greater than the depth of the lightly doped region; a gate oxide layer on the silicon substrate; and a notched gate electrode on the substrate, the notched gate electrode including a notch along an outer side surface of a lower portion such that a top portion of the notched gate electrode is wider than the lower portion, the gate oxide layer extending between the interface of the notched gate electrode and the substrate, and a gate poly oxide layer provided along an outer side surface of the notched gate electrode and along an inner wall of the notch, a portion of the lightly doped region being under the notch.
    Type: Application
    Filed: April 2, 2002
    Publication date: October 3, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyuk-Ju Ryu, Young-Gun Ko
  • Publication number: 20020119608
    Abstract: The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions.
    Type: Application
    Filed: April 29, 2002
    Publication date: August 29, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Gun Ko, Byung-Sun Kim, Young-Wug Kim
  • Patent number: 6407429
    Abstract: The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: June 18, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Gun Ko, Byung-Sun Kim, Young-Wug Kim
  • Publication number: 20010031518
    Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.
    Type: Application
    Filed: February 13, 2001
    Publication date: October 18, 2001
    Applicant: Samsung Electronics,Co. LTD
    Inventors: Young-Wug Kim, Byung-Sun Kim, Hee-Sung Kang, Young-Gun Ko, Sung-Dae Park, Min-Su Kim, Kwang-Il Kim