Abstract: The present disclosure describes a circuit for managing power and heat. The circuit includes a motherboard voltage regulator to supply a current to a loadline. The circuit includes a sense point coupled to the loadline, the circuit to measure a sensed voltage at the sense point. The circuit also includes a comparator to compare the sensed voltage to a reference voltage. An output of the comparator is used to indicate a level of current being provided by the motherboard voltage regulator.

Abstract: A method of operating an electronic device is provided. The method includes communicating data with a wireless network using a wireless communication, connecting to an external electronic device using a wired communication, exchanging data with the external device at a first data throughput using the wired communication while performing the wireless communication, and changing the first data throughput to a second data throughput while performing the wireless communication.

Abstract: Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated circuit. A floorplan associated with the functional description is modified to create a modified floorplan. The modified floorplan has a physical design change relative to the floorplan. A pre-route is automatically generated based on receipt of the routing selection and the modified floorplan. The pre-route is added to a physical design of the chip to create a pre-routed physical design. Additional methods and systems are disclosed.

Abstract: Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated circuit. A floorplan associated with the functional description is modified to create a modified floorplan. The modified floorplan has a physical design change relative to the floorplan. A pre-route is automatically generated based on receipt of the routing selection and the modified floorplan. The pre-route is added to a physical design of the chip to create a pre-routed physical design. Additional methods and systems are disclosed.

Abstract: In general, in one aspect, the disclosure describes a delay locked loop (DLL) with a regenerative delay line that includes a cascade of delay stages. A first delay stage includes a two-input delay device which receives a 180 degree phase shifted signal as feedback. This feedback signal configures the delay line into a regenerative amplifier, the frequency response of which has peaking or resonance at the input frequency which results in jitter filtering. The amount of regeneration is determined by relative strength of an input signal and the feedback signal. Relative strength is determined by relative size of devices receiving the signals. The resonant frequency (with or without oscillations) of the delay line may automatically be tuned to the incoming clock frequency by the DLL control loop. Each of the other delay stages may include two-input delay devices with the inputs shorted for uniformity.

Abstract: In general, in one aspect, the disclosure describes a delay line including a cascade of delay stages where each stage delays the phase a defined amount. Each delay stage includes an active voltage control delay element and one or more passive delay elements (e.g., resistive-capacitive (RC) networks). The aggregate amplitude gain roll-off of an active/passive multi pole delay stage delaying the phase a defined amount is less than the amplitude gain roll-off of a single pole delay stage delaying the phase the defined amount. Accordingly jitter amplification of the active/passive multi pole delay stage is less than that of a single pole delay stage. The power consumption of an active/passive multi pole delay stage is less than an all active multi pole delay stage.

Abstract: Embodiments of a phase interpolator for a phase-locked loop are presented herein.

Abstract: A first oscillatory signal is distributed to a number of destinations in an integrated circuit die. The frequency of a second oscillatory signal is made to track the average frequency of the first oscillatory signal, using an injection locked oscillator, as such rejecting high frequency jitter. The second oscillatory signal is provided to one or more of the destinations. Other embodiments are also described and claimed.