Abstract: A semiconductor device includes a first transistor element having a first channel region and a second transistor element having a second channel region, wherein the first channel region includes a first crystalline silicon/germanium (Si/Ge) material mixture having a first germanium concentration, and wherein the second channel region includes a second crystalline Si/Ge material mixture having a second germanium concentration that is higher than the first germanium concentration.

Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.

Abstract: A semiconductor device includes a first transistor element having a first channel region and a second transistor element having a second channel region, wherein the first channel region includes a first crystalline silicon/germanium (Si/Ge) material mixture having a first germanium concentration, and wherein the second channel region includes a second crystalline Si/Ge material mixture having a second germanium concentration that is higher than the first germanium concentration.

Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.

Abstract: When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material for defining the silicided portions may be omitted during the process sequence, for instance, by using a patterned liner material or by applying a process strategy for removing the metal material from resistor areas that may not receive a corresponding metal silicide. By implementing the corresponding process strategies, semiconductor devices may be obtained with reduced probability of contact failures, with superior performance due to relaxing surface topography upon forming the contact level, and/or with increased robustness with respect to contact punch-through.

Abstract: When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material for defining the silicided portions may be omitted during the process sequence, for instance, by using a patterned liner material or by applying a process strategy for removing the metal material from resistor areas that may not receive a corresponding metal silicide. By implementing the corresponding process strategies, semiconductor devices may be obtained with reduced probability of contact failures, with superior performance due to relaxing surface topography upon forming the contact level, and/or with increased robustness with respect to contact punch-through.

Abstract: A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure.

Abstract: A method of manufacturing a trench isolation of a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, forming a trench through the semiconductor layer and extending at least partially into the buried oxide layer, forming a liner at sidewalls of the trench, deepening the trench into the semiconductor bulk substrate, filling the deepened trench with a flowable dielectric material, and performing an anneal of the flowable dielectric material.

Abstract: A semiconductor device is provided comprising a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and a transistor device, wherein the transistor device comprises a gate electrode formed by a part of the semiconductor bulk substrate, a gate insulation layer formed by a part of the buried oxide layer and a channel region formed in a part of the semiconductor layer.

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region.

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region.

Abstract: A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure.

Abstract: Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.

Abstract: Disclosed herein are various methods of forming a gate cap layer above a replacement gate structure, and a device having such a cap layer. In one example, a device disclosed herein includes a replacement gate structure having a dished upper surface, sidewall spacers positioned proximate the replacement gate structure and a gate cap layer positioned above the replacement gate structure, wherein the gate cap layer has a bottom surface that corresponds to the dished upper surface of the replacement gate structure.

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.

Abstract: Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.

Abstract: A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems.

Abstract: Methods are provided for fabricating a semiconductor device. One embodiment includes forming an insulator layer overlying a semiconductor substrate and depositing a layer of polycrystalline silicon overlying the insulator layer. Conductivity determining impurity ions are implanted into at least an upper portion of the layer of polycrystalline silicon. At least the upper portion of the layer of polycrystalline silicon is etched using a first anisotropic etch chemistry to expose an edge portion of the upper portion. An oxide barrier is formed on the edge portion and a further portion of the layer of polycrystalline silicon is etched using the first anisotropic etch chemistry. Then a final portion of the layer of polycrystalline silicon is etched using a second anisotropic etch chemistry.

Abstract: In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.