Patents by Inventor Gunter Igel
Gunter Igel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080220541Abstract: A process for structuring a surface layer of an object includes applying bio-components to the surface of the object that carry away surface material. The bio-components are contained in at least one of a nutrient and osmotic protective medium. The at least one of a nutrient and osmotic protective medium having the bio-components contained therein is removed after the surface material is carried away from the object surface.Type: ApplicationFiled: May 14, 2008Publication date: September 11, 2008Applicant: Micronas GmbHInventors: Bernhard Wolf, Hans-Jurgen Gahle, Gunter Igel, Werner Baumann, Ralf Ehret, Mirko Lehmann
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Publication number: 20060050935Abstract: The invention relates to a fingerprint recognition module comprising a substrate consisting of a material that is electrically insulating at least on its upper side and at least partially thermally insulating. Said substrate receives a composite of structured thin films on its surface, which directly forms a measuring field on the surface of the substrate for measuring a fingerprint. Said composite consists of an array of resistive, temperature-dependent elements, and contains strip conductors which connect the resistive, temperature-dependent elements to at least one connection field located on the substrate, outside the measuring field, and form part of the composite of structured thin films.Type: ApplicationFiled: May 15, 2003Publication date: March 9, 2006Inventors: Burkhard Bustgens, Gerald Urban, Joachim Aurich, Gunter Igel
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Publication number: 20040147119Abstract: According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated into the substrate regions not covered by the masking layer (6). A heat treatment is used to diffuse the substance into a substrate region covered by the masking layer (6) such that a concentration gradient of the substance is created in the substrate region covered by the masking layer (6), proceeding from the edge of the masking layer (6) inward with increasing distance from the edge. The masking layer (6) is then removed to expose the substrate region under this layer, and a near-surface layer of the substrate (3) in the exposed substrate region is converted by a chemical conversion reaction into a coating (9) which has a layer thickness profile corresponding to the concentration gradient of the substance contained in this near-surface layer.Type: ApplicationFiled: July 28, 2003Publication date: July 29, 2004Inventors: Gunter Igel, Mirko Lehmann
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Publication number: 20040091997Abstract: A process for structuring a surface layer of an object includes applying bio-components to the surface of the object that carry away surface material. The bio-components are contained in at least one of a nutrient and osmotic protective medium. The at least one of a nutrient and osmotic protective medium having the bio-components contained therein is removed after the surface material is carried away from the object surface.Type: ApplicationFiled: October 24, 2003Publication date: May 13, 2004Applicant: Micronas GmbHInventors: Bernhard Wolf, Hans-Jurgen Gahle, Gunter Igel, Werner Baumann, Ralf Ehret, Mirko Lehmann
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Publication number: 20030173561Abstract: The invention relates to a method for producing an optical transmitting and receiving device (1, 1a) comprising a light emitting transmission element (3, 3a) and a receiving element (4, 4a) which converts this light into an electrical magnitude. The transmission and receiving elements are inserted into a silicon substrate. The optical transmitting and receiving device (1) is preferably inserted in a monolithic manner into a common substrate, comprising a sequence of superimposed layers for the light emitting transmission element (3) and the light receiving element (4). An electrically insulating intermediate layer (9, 9a) is incorporated between the transmission and receiving element.Type: ApplicationFiled: November 4, 2002Publication date: September 18, 2003Inventors: Ulrich Sieben, Gunter Igel
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Publication number: 20030148610Abstract: The invention relates to a method for producing a sensor (1), wherein a carrier chip (2) is produced. Said chip is provided with a sensor structure (3) comprising an active sensor surface (4). A material (9) capable of flowing is applied onto carrier chips (2) in such a way that the sensor structure (3) has a thinner layer thickness on said active sensor surface (4) than on the area of the carrier chip (2) which borders on the active sensor surface (4). The material (9) which is capable of flowing is hardened thereafter. The hardened material (9) is subsequently removed by chemical means from the surface which faces said carrier chip (2) until the active sensor surface of the sensor structure is layed bare.Type: ApplicationFiled: January 13, 2003Publication date: August 7, 2003Inventors: Gunter Igel, Markus Rogalla
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Publication number: 20030059936Abstract: A process is provided for the intracellular manipulation of a biological cell (3) which is positioned adhering to a support area (5) in a culture medium (2). Inside the support area (5) for the cell (3) an opening into the membrane of the cell (3) is created spaced from its support edge. The edge of the cell membrane surrounding the opening, adhering to the support area (5), thus seals off the cell fluid situated in the interior of the cell (3) from the culture medium (2) and insulates the cell fluid against the culture medium (2). The interior of the cell (3) is manipulated through the opening. An apparatus for implementing the process is also provided, including an object carrier (4) with a support area (5) for adhering the cell and a poration tool (6) for creating the opening in the cell membrane. The poration tool (6) may be any of various chemical, mechanical and/or electrical devices.Type: ApplicationFiled: July 23, 2002Publication date: March 27, 2003Applicant: Micronas GmbHInventors: Werner Baumann, Ralf Ehret, Mirko Lehmann, Gunter Igel, Hans-Jurgen Gahle, Ulrich Sieben, Ingo Freund, Martin Brischwein
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Patent number: 6460416Abstract: The invention relates to a capacitor structure with two substrates (1) each having a capacitor electrode (3) deposited on its surface, the substrates (1) being joined together by bump structures located on both sides of the capacitor electrodes (3) such that the capacitor electrodes (3) lie opposite each other and form a capacitor, the distance d between the capacitor electrodes (3) being defined by the height of the bump structures, and measuring connections (5) being provided on one of the substrates (1) for making capacitance measurements.Type: GrantFiled: July 10, 1998Date of Patent: October 8, 2002Assignee: Micronas Intermetall GmbHInventor: Gunter Igel
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Publication number: 20020110847Abstract: A method is provided for measuring a state variable of a biological cell (3) located in a nutrient medium (2) and supported on and adhering to a support area (5). Within the support area (5) for the cell (3) and at a distance from the support area edge, an opening is made in the membrane of the cell (3). The edge of the cell membrane that surrounds the opening and adheres to the support area (5) seals off the liquid found inside the cell (3) from the nutrient medium (2). Through the opening the state variable (2) is measured. An apparatus for performing the method is also provided.Type: ApplicationFiled: April 9, 2002Publication date: August 15, 2002Applicant: Micronas GmbHInventors: Werner Baumann, Ralf Ehret, Mirko Lehmann, Gunter Igel, Hans-Jurgen Gahle, Berhard Wolf, Ulrich Sieben, Ingo Freund, Martin Brischwein
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Publication number: 20010018232Abstract: A process for manufacturing a semiconductor arrangement (3), whereby in particular a wafer (1) with a large number of semiconductor arrangements forming chips (7) is manufactured, and the wafer is divided afterward, and in this way the semiconductor arrangements are separated. At least one region of a wafer side is covered by a passivation layer (9) during the etching of the remaining wafer area. After etching, the passivation layer (9) is removed. At least in an outer edge region of the wafer, if need be additionally in the shape of the wafer front side, outside the active chip surface and especially in the regions bounding the respective chip systems, adhesion zones (8) for the passivation layer (9) are created which enter into a sealing, and in particular a chemical combination with the material used for the passivation layer.Type: ApplicationFiled: December 21, 2000Publication date: August 30, 2001Inventor: Gunter Igel
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Patent number: 5976901Abstract: The invention relates to a process for manufacturing semiconductor devices with active device structures which are connected with one another in a wafer, the area of a semiconductor device being determined by process parameters and being substantially greater than the area of an active device structure. An improvement of the process is achieved by forming several like active device structures on each of the semiconductor devices.Type: GrantFiled: February 21, 1997Date of Patent: November 2, 1999Assignee: General Semiconductor Inc.Inventor: Gunter Igel
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Patent number: 5944976Abstract: A process for forming adjacent moats or holes in an electrically non-insulating substrate wherein an electrically insulating masking layer is deposited on the substrate. To form two adjacent moats or holes, the masking layer has an opening whose width is chosen so that it extends over a part of the overall width of the two moats or holes to be formed, and whose shape corresponds to the shape of the moats or holes to be formed. The surface of the masked substrate is then subjected to an anodic oxidation, with the oxidation voltage chosen to be so high that two adjacent moats or holes are formed per opening in the masking layer.Type: GrantFiled: January 15, 1997Date of Patent: August 31, 1999Assignee: Micronas Intermetall GmbHInventor: Gunter Igel
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Patent number: 5933715Abstract: A process for manufacturing discrete electronic devices with active structures in an SOI (silicon-on-insulator) substrate which is thickened by an epitaxial layer and whose surface has a <100> orientation, said process comprising the steps of: anisotropically etching the first silicon layer to form a moat having a diameter tapering in the direction of the insulator layer, said moat extending to the insulator layer; forming an insulating layer on the sidewalls of the moat; removing a portion of the insulator layer adjoining the moat to expose a portion of the second silicon layer, which is separated from the first silicon layer by the insulator layer; forming the active structure in the second silicon layer below the portion of the insulator layer which was removed; and depositing a contact layer on the insulating layer and the active element for making contact to the active structure.Type: GrantFiled: March 7, 1997Date of Patent: August 3, 1999Assignee: Micronas Intermetall GmbHInventors: Gunter Igel, Ruediger Joachim Stroh
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Patent number: 5890807Abstract: A method identifying components is disclosed. Measured values of a randomly produced property of the component are recorded. The measured values are biuniquely assigned to the component by means of a characteristic parameter and the measured values accessibly storing the measured values, or a unique code assigned thereto. Further, the characteristic parameter are accessibly stored.Type: GrantFiled: October 22, 1996Date of Patent: April 6, 1999Assignee: Deutsche ITT Industries GmbHInventors: Gunter Igel, Siegfried Heinrich
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Patent number: 5885897Abstract: A process is disclosed for making contact to differently doped regions in a semiconductor device which are disposed in a silicon substrate in different depths, a first region with a first dopant concentration and/or conductivity type and the smaller depth being disposed in a second region with a second dopant concentration and/or conductivity type and the greater depth, and a first metal layer being deposited on the first region. A second metal layer is deposited on a portion of the first metal layer, and the structure is subjected to a heat treatment in which contact is made to the first region through the first metal layer and to the second region through the first metal layer and the second metal layer.Type: GrantFiled: January 10, 1997Date of Patent: March 23, 1999Assignee: Deutsche ITT Industries GmbHInventor: Gunter Igel
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Patent number: 5858808Abstract: An auxiliary device is constituted by a U-bolt-shaped, pincer-like implement which, during the fabrication of semiconductor devices with a mesa structure from a starting substrate forming a wafer, serves to transfer the outline geometry of the individual semiconductor devices from one side of the wafer to the back of the wafer. The implement has at least one tracer at the end of one of its arms for engaging a sawed groove and for guiding the implement along the sawed groove on one side of the wafer. At the end of the other arm, a marking device with at least one marking stylus is provided whereby the course of the at least one sawed grooved can be transferred from the front side of the wafer to the back, and scribed there in the form of auxiliary lines.Type: GrantFiled: January 15, 1997Date of Patent: January 12, 1999Assignee: Deutsche ITT Industries GmbHInventors: Gunter Igel, Johann Schroeder
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Patent number: 5824595Abstract: A method for separating elements associated within a body includes creating a separation region within the body, between the elements, leaving a region of the body which is to be thinned. The method then requires depositing a delay layer on the body, with an opening around the separation region. The delay layer has a predetermined removal rate relative to the removal rate of the body. Lastly, the method requires removing a predetermined amount of the delay layer, the separation region, and the region of the body to be thinned. Preferably, the removing is accomplished by etching, such as plasma etching, and the etch rate of the delay layer is lower than the etch rate for the separation region. In a preferred method, the predetermined removal rate and the positions of the openings in the delay layer are selected so that upon after etching, the elements remaining have a predetermined locus dependent thickness.Type: GrantFiled: October 3, 1996Date of Patent: October 20, 1998Assignee: Deutsche ITT Industries GmbHInventors: Gunter Igel, Martin Mall
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Patent number: 5789307Abstract: A method of separating electronic devices contained in a carrier which are provided at the surface of the carrier and are covered by a protective layer. Openings are provided above separation regions between adjacent electronic devices. The material of the carrier is removed in the separation regions starting from the openings, and the electronic devices are, at least during the material-removing process, confined in the carrier by respective regions with a material removal property different from that of the carrier.Type: GrantFiled: February 7, 1997Date of Patent: August 4, 1998Assignee: Deutsche ITT Industries GmbHInventors: Gunter Igel, Martin Mall