Abstract: A measuring device (1) has a semiconductor arrangement, which includes a semiconductor chip (2) connected to a carrier (4) having at least one through-hole (3). The semiconductor chip (2) has at least one sensor (6) with an active sensor surface (5) facing the through-hole (3). The semiconductor chip (2) has electrical terminal points (9), which are connected using flip-chip connections (10) to terminal contacts (11) facing the terminal points (9) and located on the carrier (4). The carrier (4) has electrical strip conductors (12), which connect the terminal contacts (11) to contact elements (13) located on the carrier. To the rear side of the carrier (4) having the contact elements (13) a strip conductor carrier (16) is provided, which has strip conductors (12) connected to opposing contacts (14). The opposing contacts (14) are each electrically connected using flip-chip connections (17), to a contact element (13), which are allocated to each of them.

Abstract: In a process for manufacturing an electrode (1) on a substrate (2) using a conventional structuring process, an electrically conducting surface structure is created which has at least one tip (3) or edge (4). In the area of the tip (3) or edge (4), an electrode layer (5) is galvanized onto the substrate (2) and/or applied by electrostatic powder coating. Then, a surface area of the substrate (2), which surrounds the electrode layer (5) located on the tip (3) or edge (4), is converted into an insulating layer (8) by a chemical reaction. The electrode layer (5) can also be applied in a manner where, in the area of the tip (3) or edge (4), a chemical is released, which upon irradiation by electromagnetic and/or particle radiation, precipitates an electrically conducting material. This chemical is then impinged in the area of the tip (3) or edge (4) with optical radiation.

Abstract: A semiconductor component (1) has a pressure sensor and a semiconductor chip (2) with a semiconductor structure (3) for at least one additional function of the semiconductor component (1). The semiconductor chip (2) is connected to a casing (5) by means of an elastic carrier arrangement (4) and can be deflected relative to the casing (5) against the restoring force of the material of the carrier arrangement (4) on the whole. For indirect measurement of a pressure acting on the semiconductor chip (2) and causing the deflection of the semiconductor chip (2), at least one position sensor that works together with the semiconductor chip (2) is provided.

Abstract: A method is provided for measuring a state variable of a biological cell (3) located in a nutrient medium (2) and supported on and adhering to a support area (5). Within the support area (5) for the cell (3) and at a distance from the support area edge, an opening is made in the membrane of the cell (3). The edge of the cell membrane that surrounds the opening and adheres to the support area (5) seals off the liquid found inside the cell (3) from the nutrient medium (2). Through the opening the state variable (2) is measured. An apparatus for performing the method is also provided.

Abstract: A coupling (1) has a coupling receiver (2) and a coupling counterpart (3) connectable with it, which in the coupling position is held in a receiver depression (6) of the coupling receiver. The receiver depression (6) is arranged in a layer stack (4) with at least two layers (5a, 5b, 5c, 5d, 5e). Proceeding from the flat surface of the layer stack (4) bordering upon the recess depression (6) to the interior of the receiver depression (6), the lateral boundary wall of the recess depression (6) has at least one cutback, which is formed by a receding layer (5a, 5c) or a receding layer area. The coupling counterpart (3) has at least one lateral guide and/or locking projection (9a, 9b), which engages into a cutback (8a, 8b) of the component (2) in the coupling position.

Abstract: In a process for coating a substrate, a texture (4) is created in a portion of its surface. A first layer (5) to be applied on the surface of the substrate adheres better to the texture (4) than it does to a surface area located outside of the texture (4). Then, the layer (5) is applied to the surface of the substrate and after that, areas of the layer projecting laterally beyond the texture (4) are mechanically removed. The material of the texture (4) contains at least one chemical element or a compound, which the layer (5) does not have or has only in a smaller concentration than the material of the texture (4). On the first layer (5), at least one second layer (7) is then applied which does not have the chemical element or compound contained in the material of the texture (4), or it has it only in a smaller concentration than the material of the texture (4).

Abstract: A chip arrangement (1) has a substrate board (2) with an opening (3), into which a carrier chip (4) is inserted, which has an electrical or electronic structural component (5). At least one conductor path (7) is integrated into the carrier chip (4), which connects the structural component (5) to the electrical connection contact (8). The carrier chip (4) is inserted into the opening (3) in such a way that its ends project beyond the opposite-facing, flat-sided surfaces (9, 9′) of the substrate board (2), and thereby form overhangs (10, 10′). Here, the structural component is arranged on the overhang (10) projecting beyond the one surface (9), and the connection contact (8) is arranged on the overhang (10′) projecting beyond the other surface (9′), and the conductor path (7) connecting the structural component (5) and the connection contact (8) passes through the opening (3). A seal is arranged between the substrate board (2) and the carrier chip (4).

Abstract: A process for manufacturing a semiconductor arrangement (3), whereby in particular a wafer (1) with a large number of semiconductor arrangements forming chips (7) is manufactured, and the wafer is divided afterward, and in this way the semiconductor arrangements are separated. At least one region of a wafer side is covered by a passivation layer (9) during the etching of the remaining wafer area. After etching, the passivation layer (9) is removed. At least in an outer edge region of the wafer, if need be additionally in the shape of the wafer front side, outside the active chip surface and especially in the regions bounding the respective chip systems, adhesion zones (8) for the passivation layer (9) are created which enter into a sealing, and in particular a chemical combination with the material used for the passivation layer.

Abstract: A semiconductor component (1a) has a highly-doped substrate (4) of a first type of doping into which a highly-doped layer (15) of a second type of doping is introduced in some areas to form a pn Zener junction (16), and a low-doped area (17) of the second type of doping extends from this highly-doped layer (15) in the substrate (4) into an epitaxial layer (5) as far as the substrate (4) of the epitaxial layer (5). A Schottky metal (11) at least partially covering the low-doped, diffused area (17) is applied to the side of the epitaxial layer (5) facing away from the substrate (4) to form a Schottky junction (18) between this area (17) and the Schottky metal (11) and another Schottky junction (13) between the Schottky metal and the epitaxial layer (5). Due to the series connection of the oppositely polarized Zener diode and Schottky diode, a low temperature coefficient is achieved.

Abstract: A process is provided for manufacturing a layer arrangement (1) having a bump for a flip chip or similar connection. The layer arrangement has a plurality of layers (2, 3, 4, 5, 6, 7, 11) made of solid material and stacked into a layer stack (8). A recess (10) that extends over several layers (2, 3, 4, 5, 6, 7, 11) is made in the layer stack (8) transverse to the coating planes of the layers (2, 3, 4, 5, 6, 7, 11). A bump material (14) is placed in the recess (10). A profiling is created on the lateral boundary wall of the recess (10) by removal of layer material of different layers (2, 3, 4, 5, 6, 7, 11) of the layer stack (8). The profiling, starting from the surface (9) of the layer stack (8) and progressing in layers to the inside of the recess (10), has at least two indentations (12) and at least one projection (13) located between them. After the production of the profiling, a bump material (14) is brought into the recess (10) in such a way that it grasps behind the indentations (12).

Abstract: The invention relates to a process for manufacturing semiconductor devices with active device structures which are connected with one another in a wafer, the area of a semiconductor device being determined by process parameters and being substantially greater than the area of an active device structure. An improvement of the process is achieved by forming several like active device structures on each of the semiconductor devices.

Abstract: A process for forming adjacent moats or holes in an electrically non-insulating substrate wherein an electrically insulating masking layer is deposited on the substrate. To form two adjacent moats or holes, the masking layer has an opening whose width is chosen so that it extends over a part of the overall width of the two moats or holes to be formed, and whose shape corresponds to the shape of the moats or holes to be formed. The surface of the masked substrate is then subjected to an anodic oxidation, with the oxidation voltage chosen to be so high that two adjacent moats or holes are formed per opening in the masking layer.

Abstract: A process for manufacturing discrete electronic devices with active structures in an SOI (silicon-on-insulator) substrate which is thickened by an epitaxial layer and whose surface has a <100> orientation, said process comprising the steps of: anisotropically etching the first silicon layer to form a moat having a diameter tapering in the direction of the insulator layer, said moat extending to the insulator layer; forming an insulating layer on the sidewalls of the moat; removing a portion of the insulator layer adjoining the moat to expose a portion of the second silicon layer, which is separated from the first silicon layer by the insulator layer; forming the active structure in the second silicon layer below the portion of the insulator layer which was removed; and depositing a contact layer on the insulating layer and the active element for making contact to the active structure.

Abstract: A method identifying components is disclosed. Measured values of a randomly produced property of the component are recorded. The measured values are biuniquely assigned to the component by means of a characteristic parameter and the measured values accessibly storing the measured values, or a unique code assigned thereto. Further, the characteristic parameter are accessibly stored.

Abstract: A process is disclosed for making contact to differently doped regions in a semiconductor device which are disposed in a silicon substrate in different depths, a first region with a first dopant concentration and/or conductivity type and the smaller depth being disposed in a second region with a second dopant concentration and/or conductivity type and the greater depth, and a first metal layer being deposited on the first region. A second metal layer is deposited on a portion of the first metal layer, and the structure is subjected to a heat treatment in which contact is made to the first region through the first metal layer and to the second region through the first metal layer and the second metal layer.

Abstract: An auxiliary device is constituted by a U-bolt-shaped, pincer-like implement which, during the fabrication of semiconductor devices with a mesa structure from a starting substrate forming a wafer, serves to transfer the outline geometry of the individual semiconductor devices from one side of the wafer to the back of the wafer. The implement has at least one tracer at the end of one of its arms for engaging a sawed groove and for guiding the implement along the sawed groove on one side of the wafer. At the end of the other arm, a marking device with at least one marking stylus is provided whereby the course of the at least one sawed grooved can be transferred from the front side of the wafer to the back, and scribed there in the form of auxiliary lines.

Abstract: A method for separating elements associated within a body includes creating a separation region within the body, between the elements, leaving a region of the body which is to be thinned. The method then requires depositing a delay layer on the body, with an opening around the separation region. The delay layer has a predetermined removal rate relative to the removal rate of the body. Lastly, the method requires removing a predetermined amount of the delay layer, the separation region, and the region of the body to be thinned. Preferably, the removing is accomplished by etching, such as plasma etching, and the etch rate of the delay layer is lower than the etch rate for the separation region. In a preferred method, the predetermined removal rate and the positions of the openings in the delay layer are selected so that upon after etching, the elements remaining have a predetermined locus dependent thickness.

Abstract: A method of separating electronic devices contained in a carrier which are provided at the surface of the carrier and are covered by a protective layer. Openings are provided above separation regions between adjacent electronic devices. The material of the carrier is removed in the separation regions starting from the openings, and the electronic devices are, at least during the material-removing process, confined in the carrier by respective regions with a material removal property different from that of the carrier.