Abstract: According to embodiments of the present invention, a photodetector is provided. The photodetector includes a substrate, a waveguide formed on a surface of the substrate, a first metal layer formed on a first side of the waveguide, wherein a first interface is defined between the waveguide and the first metal layer, and a silicide layer formed on a second side of the waveguide, wherein a second interface is defined between the waveguide and the silicide layer, and wherein the second side is opposite to the first side, and wherein at least one of the first interface and the second interface is at least substantially perpendicular to the surface of the substrate. Various embodiments further provide a method of forming the photodetector.

Abstract: In an embodiment, a phase shifting device may be provided. The phase shifting device may include a supporting layer and a semiconducting layer disposed above the supporting layer. The semiconducting layer may include a first doped region doped with doping atoms of a first conductivity type and arranged on the supporting layer; and a second doped region doped with doping atoms of a second conductivity type being different from the first conductivity type; wherein the second doped region may be disposed over the first doped region such that a first doped regions junction may be formed in a direction substantially parallel to a surface of the supporting layer and a second doped regions junction may be formed in a direction substantially perpendicular to the surface of the supporting layer. A method of forming a phase shifting device and an electro-optic device may also be provided.

Abstract: According to embodiments of the present invention, an optical sensing system is provided. The optical sensing system includes a resonator arrangement including a first resonator, wherein an effective refractive index of the first resonator is changeable in response to a change in a refractive index of a cladding of the first resonator, and a second resonator to which a current or voltage being adjustable in response to a change in the effective refractive index of the first resonator is applied, wherein the optical sensing system is configured to determine the change in the effective refractive index of the first resonator based on a change in the current or voltage applied to the second resonator. Further embodiments provide a method of determining a change in an effective refractive index of a resonator of an optical sensing system.

Abstract: According to embodiments of the present invention, an optical modulator is provided. The optical modulator includes a depletion region comprising a junction between from a first conductivity type portion and a second conductivity type portion, a first intrinsic region, and a second intrinsic region, and wherein the depletion region is disposed between the first intrinsic region and the second intrinsic region.

Abstract: According to embodiments of the present invention, a light emitting device is provided. The light emitting device includes: an active region comprising at least one p-i-n junction, the at least one p-i-n junction comprising a p-doped region, an intrinsic region and an n-doped region; a first contact; and a second contact, wherein the active region is disposed between the first contact and the second contact; and wherein a voltage applied to the first contact and the second contact produces a current configured to flow between the first contact and the second contact in a direction substantially parallel to a surface of the intrinsic region of the active region configured to emit a light. According to embodiments of the present invention, the intrinsic region includes a multiple quantum well (MQW) such that a current injected flows laterally in a direction substantially parallel to the surface of the wells of the MQW.

Abstract: Embodiments provide an optical device including a carrier; a light source; a receiving chamber in or on the carrier wherein the receiving chamber is configured to receive an optical element; the optical element received in the receiving chamber; a plurality of actuators; and a waveguide arranged to receive light transmitted from the light source through the optical element. At least one of the receiving chamber and the actuators is arranged and configured to adjust the position of the optical element in the receiving chamber in a first direction perpendicular to the main surface of the carrier and in a second direction in-plane with the main surface of the carrier.

Abstract: An electro-optic device is disclosed. The electro-optic device includes an insulating layer, a first semiconducting region disposed above the insulating layer and being doped with doping atoms of a first conductivity type, a second semiconducting region disposed above the insulating layer and being doped with doping atoms of a second conductivity type and an electro-optic active region disposed above the insulating layer and between the first semiconducting region and the second semiconducting region.

Abstract: An embodiment of the invention relates to an optical resonator. The optical resonator includes an input optical waveguide and a closed loop coupled to the input optical waveguide. The closed loop is adapted to receive light from the input optical waveguide, wherein the closed loop includes at least one hole formed within a portion of the closed loop.

Abstract: According to an embodiment, a photodetector is provided, including a detector region, a first contact region forming an interface with the detector region, and a first valence mending adsorbate region between the first contact region and the detector region.

Abstract: A memory cell is provided. The memory cell comprises a first wire shaped channel structure; and a charge trapping structure surrounding the perimeter surface of the first wire shaped channel structure, the charge trapping structure comprising two charge trapping partial to structures, wherein each charge trapping partial structure is formed of a different material capable of storing electrical charges. Methods of manufacturing the memory cell are also provided.

Abstract: A silicon-germanium nanowire structure arranged on a support substrate is disclosed, The silicon-germanium nanowire structure includes at least one germanium-containing supporting portion arranged on the support substrate, at least one germanium-containing nanowire disposed above the support substrate and arranged adjacent the at least one germanium-containing supporting portion, wherein germanium concentration of the at least one germanium-containing nanowire is higher than the at least one germanium-containing supporting portion. A transistor comprising the silicon-germanium nanowire structure arranged on a support substrate is also provided. A method of forming a silicon-germanium nanowire structure arranged on a support substrate and a method of forming a transistor comprising forming the silicon-germanium nanowire structure arranged on a support substrate are also disclosed.

Abstract: The wafer arrangement (100) provided comprises a first wafer (101), which comprises an integrated circuit and a recess (105). The wafer arrangement further comprises a portion of a second wafer (103), which comprises a carrier portion and a protrusion (107), the protrusion comprising an active component or actively controlled component (109) such as a MEMS component, wherein the portion of the second wafer (103) is coupled to the first wafer (101) such that the protrusion (107) is received in the recess (105). The invention provides a mechanism for accurately aligning an active component (109) on the second wafer (103) with components on the first wafer (101), such as photonic, electronic or optical components.

Abstract: A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.

Abstract: A method for fabricating a MOSFET structure is disclosed. A coating is provided on the upper surface of a gate. Thereafter doped regions are implanted into the substrate. A layer is provided over the MOSFET structure and etched to form spacers. The MOSFET structure is reacted with salicide-forming reactant to produce a salicide MOSFET.

Abstract: A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.

Abstract: Disclosed are methods and systems for forming salicide, in which a semiconductor substrate is provided with at least one exposed silicon surface. The semiconductor substrate is placed into a sputtering chamber. A silicide-forming metal layer, formed of a metal such as Co, Ni, is sputter-deposited over the exposed silicon surface. A process temperature is controlled below room temperature during the sputter deposition and preferably between approximately 0° C. to 10° C. The silicide-forming metal layer formed on the exposed silicon surface is first annealed to convert the silicide-forming metal layer into a salicide layer. Also, the system of the present invention is comprised of a sputter chamber including a mount for mounting a semiconductor substrate and a cooling mechanism coupled with the mount for cooling the semiconductor substrate. The cooling mechanism includes a controller to maintain a process temperature below room temperature.

Abstract: A novel gate structure and a method of forming the same for a self-aligned contact on a semiconductor substrate. The method includes forming a gate oxide layer on the semiconductor substrate. Then a first conductive layer is formed on the gate oxide layer. Next, a second conductive layer, preferably a refractory metal silicide (e.g. WSix), is formed overlying the first conductive layer. A capping layer is formed overlying the second conductive layer. Then the capping layer is etched to form a patterned capping layer having a lower outside corner. An upper portion of the second conductive layer is selectively dry etched laterally to form a lateral recess under the capping layer to increase etch margin. A lower portion of the second conductive layer is then etched anisotropically down to the first conductive layer along a sidewall approximately vertically aligned with the lower outside corner of the patterned capping layer.

Abstract: Methods for forming nitrided oxides in semiconductor devices by rapid thermal oxidation, in which a semiconductor substrate having an exposed silicon surface is placed into a thermal process chamber. Then, an ambient gas comprising N2O and an inert gas such as argon or N2 is introduced into the process chamber. Next, the silicon surface is heated to a predefined process temperature, thereby oxidizing at least a portion of the silicon surface. Finally, the semiconductor substrate is cooled. An ultra-thin oxide layer with uniform oxide characteristics, such as more boron penetration resistance, good oxide composition and thickness uniformity, increased charge to breakdown voltage in the oxide layer, can be formed.

Abstract: The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased.

Abstract: The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased.