Abstract: A method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer. The silicon layer has a substantially uniform thickness. The silicon layer is polished to smooth the silicon layer such that the thickness is substantially uniform after polishing.

Abstract: A method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer. The silicon layer has a substantially uniform thickness. The silicon layer is polished to smooth the silicon layer such that the thickness is substantially uniform after polishing.

Abstract: A method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer. The silicon layer has a substantially uniform thickness. The silicon layer is polished to smooth the silicon layer such that the thickness is substantially uniform after polishing.

Abstract: A method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer. The silicon layer has a substantially uniform thickness. The silicon layer is polished to smooth the silicon layer such that the thickness is substantially uniform after polishing.

Abstract: A silicon-on-insulator or bonded wafer includes an upper portion having a trapezoid shape in cross-section and a lower portion having an outer peripheral edge having a curved shape.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: A method for manufacturing a silicon-on-insulator structure including a substrate wafer, an active wafer, and an oxide layer between the substrate wafer and the active wafer. The method includes the steps of heat treating the structure, trapezoid grinding edges of the wafer, and grinding a surface of the wafer.

Abstract: A silicon-on-insulator or bonded wafer includes an upper portion having a trapezoid shape in cross-section and a lower portion having an outer peripheral edge having a curved shape.

Abstract: A grinding tool for trapezoid grinding of a wafer on a profiling machine includes an annular wheel including a central hole adapted for mounting the wheel on a spindle. The wheel includes at least two grooves disposed at an outer edge of the wheel and the grooves are sized for receiving an outer edge of the wafer. At least one of the grooves is adapted for rough grinding of the wafer. At least one other of the grooves is adapted for fine grinding of the wafer.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water, a hydroxide ion source, and a chelating agent. The process produces silicon wafers substantially free from diffused metal ions.

Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water, a hydroxide ion source, and a chelating agent. The process produces silicon wafers substantially free from diffused metal ions.

Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water and a source of hydroxide ions and generally characterized by a lower concentration of water and/or higher concentration of source of hydroxide ions. In accordance with another embodiment, the caustic etchant includes a salt additive. The process produces silicon wafers with improved surface characteristics such as flatness and nanotopography.

Abstract: A method of manufacturing a semiconductor wafer includes providing an ingot of semiconductor material, slicing the wafer from the ingot, and processing the wafer to increase parallelism of the front surface and the back surface. A final polishing operation on at least the front surface is performed by positioning the wafer between a first pad and a second pad and obtaining motion of the front and back surfaces of the wafer relative to the first and second pads to maintain parallelism of the front and back surfaces and to produce a finish on at least the front surface of the wafer so that the front surface is prepared for integrated circuit fabrication. In another aspect, the wafer is rinsed by a rinsing fluid to increase hydrodynamic lubrication. Other methods are directed to conditioning the polishing pad and to handling wafers after polishing. An apparatus for polishing wafers is also included.

Abstract: A method for polishing front and back surfaces of a semiconductor wafer includes the step of providing a polishing apparatus having a wafer carrier generally disposed between a first polishing pad and a second polishing pad. The first pad has a hardness significantly greater than a hardness of the second pad. The wafer is placed in the wafer carrier so that the front surface faces the first pad and so that the back surface faces the second pad. A polishing slurry is applied to at least one of the pads and the carrier, first pad and second pad are rotated. The front surface is brought into contact with the first pad and the back surface is brought into contact with the second pad for polishing the front and back surfaces of the wafer whereby less wafer material is removed from the back surface engaged by the second pad and the back surface has less gloss than the front surface after polishing so that the front surface and back surface are visually distinguishable.

Abstract: A method for repairing a wafer carrier after plural processing operations during which the carrier holds a plurality of semiconductor wafers in a processing apparatus which removes wafer material by at least one of abrading and chemical reaction. The wafer carrier has holes for receiving respective ones of the wafers and removable annular inserts for each hole. Each insert is receivable in a respective one of the holes for engaging a peripheral edge of one of the wafers. The thickness of the insert is reduced during the successive processing operations. The method includes removing at least one of the inserts from the wafer carrier and installing at least one new insert in the wafer carrier having a thickness substantially greater than a minimum thickness to extend the useful life of the wafer carrier and to improve the flatness and parallelism of surfaces of wafers processed using the wafer carrier.

Abstract: A method of manufacturing a semiconductor wafer includes providing an ingot of semiconductor material, slicing the wafer from the ingot, and processing the wafer to increase parallelism of the front surface and the back surface. A final polishing operation on at least the front surface is performed by positioning the wafer between a first pad and a second pad and obtaining motion of the front and back surfaces of the wafer relative to the first and second pads to maintain parallelism of the front and back surfaces and to produce a finish on at least the front surface of the wafer so that the front surface is prepared for integrated circuit fabrication. In another aspect, the wafer is rinsed by a rinsing fluid to increase hydrodynamic lubrication. Other methods are directed to conditioning the polishing pad and to handling wafers after polishing. An apparatus for polishing wafers is also included.