Abstract: A process for preparing a passivated emitter rear contact solar cell, which includes the steps as follows: removing the damaged layer on the surface of the silicon wafer and at the same time polishing both surfaces, texturing, forming PN junction, etching, removing the glass impurity, depositing a passivation film on the back surface, depositing a passivating antireflective layer on the front surface, making local openings on the back surface, screen printing of metal paste on both the front surface and the back surface and sintering, in which the texturing step employs a catalytic metal etching approach, and the textured structure is a nanometer-level textured structure. The present invention has combined removing the damaged layer on the surface of the silicon wafer and polishing both the front and back surfaces into one single step, and thus has simplified the production process and reduced the production cost.

Abstract: A method for producing a textured structure of a crystalline silicon solar cell is provided, including the following steps: (1) forming a porous layer structure on a surface of a silicon wafer; (2) then cleaning with a first alkaline chemical solution; (3) removing residual metal particles with a cleaning solution; (4) and then etching the surface with a first chemical etching solution to obtain the textured structure of the crystalline silicon solar cell. The method greatly prolongs the lifetime of the mixed solution of hydrofluoric acid and nitric acid and ensures the stability and uniformity of the textured structure.

Abstract: A textured structure of a crystalline silicon solar cell that is mainly constructed by a plurality of micro-structures similar to inverted pyramids; the lower part of the micro-structure similar to the inverted pyramid is an inverted pyramidal structure, and the upper part thereof is an inverted circular truncated conical structure; and the top of the micro-structure similar to the inverted pyramid is selected from one or more of a circle, an oval, or a closed figure enclosed by multiple curves. Experiments prove that the conversion efficiency of a cell piece may be improved by 0.25-0.4%, thereby obtaining unexpected effects.

Abstract: A process for preparing a passivated emitter rear contact solar cell, which includes the steps as follows: removing the damaged layer on the surface of the silicon wafer and at the same time polishing both surfaces, texturing, forming PN junction, etching, removing the glass impurity, depositing a passivation film on the back surface, depositing a passivating antireflective layer on the front surface, making local openings on the back surface, screen printing of metal paste on both the front surface and the back surface and sintering, in which the texturing step employs a catalytic metal etching approach, and the textured structure is a nanometer-level textured structure. The present invention has combined removing the damaged layer on the surface of the silicon wafer and polishing both the front and back surfaces into one single step, and thus has simplified the production process and reduced the production cost.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween.

Abstract: Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.

Abstract: Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

Abstract: Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.

Abstract: Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween.

Abstract: The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.

Abstract: Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

Abstract: Plasma treating a low-k dielectric layer (104) using an oxidation reaction (e.g., O2) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The plasma treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130, 132), during a rework of the pattern (130, 132), or between via and trench patterning to reduce resist poisoning.