Abstract: The present invention relates to a method for removing protein corona on the surface of nanometer particle. Specifically, the invention provides a method for removing protein corona of protein corona modified nanometer particle, the method comprises the following steps: subjecting the protein corona modified nanometer particle to ultrasound stimulation to remove the protein corona of the protein corona modified nanometer particle; the nanometer particle comprises perfluoropentane. Ultrasound stimulation can remove protein corona on the surface of nanometer particle, overcome the masking effect of the protein corona on the ligand modified on the surface of nanometer particle, and prevent the protein corona from blocking the binding of the ligand modified on the surface of nanometer particle to cell receptor.

Abstract: Disclosed is a pixel circuit arranged in a display substrate, which comprises a first driving mode and a second driving mode. Content displayed in the display substrate comprises multiple display frames. In the first driving mode and the second driving mode, the display frames comprise refresh frames. A signal of a second scanning line is the same as that of a third scanning line. The time of which the signal of the second scanning line is an active level signal comprises a first refresh time period, a second refresh time period and a third refresh time period, which sequentially occur at intervals. During the second refresh time period, a signal of a first scanning line is an inactive level signal. The voltage of a signal at a reset voltage end is a positive voltage, and the voltage of a signal at a first initial voltage end is a negative voltage.

Abstract: Provided are an ottoman linkage device, a frame body, and a seat. The ottoman linkage device includes an upper link, a lower link, a middle ottoman link, a first front ottoman link, a second front ottoman link, a first connection link, a second connection link, a front ottoman bracket, and a middle ottoman bracket. The upper link or the lower link is rotatable under a driving force to make the ottoman linkage device unfold or fold. By changing the length of the first connection link and the length of the second connection link, the magnitude of the driving force of the first connection link can be adjusted.

Abstract: The present invention relates to an amphiphilic material and an application thereof in preparation of a liposome, and in particular, the present invention provides an amphiphilic material, wherein the structure of the amphiphilic material is as follows. The amphiphilic material of the present invention is used for preparing drug-loaded nanoparticles to effectively enter cells such as tumor cells, thereby enhancing the therapeutic effect of the drug.

Abstract: A reaction-regeneration device for catalytic dehydrogenation or/and catalytic cracking of alkanes comprises a reaction device and a regeneration device. The reaction device comprises a reactor and a disengager, and the disengager is located at an upper part of the reactor. The reactor comprises a tapering section, and diameters of cross sections of the tapering section gradually decrease from bottom to top. Secondary conversion of alkenes caused by back-mixing is reduced, and thus the yield and selectivity to alkenes are increased.

Abstract: A reaction-regeneration device for catalytic dehydrogenation or/and catalytic cracking of alkanes comprises a reaction device and a regeneration device. The reaction device comprises a reactor and a disengager, and the disengager is located at an upper part of the reactor. The reactor comprises a tapering section, and diameters of cross sections of the tapering section gradually decrease from bottom to top. Secondary conversion of alkenes caused by back-mixing is reduced, and thus the yield and selectivity to alkenes are increased.

Abstract: A reaction-regeneration device for catalytic dehydrogenation or/and catalytic cracking of alkanes comprises a reaction device and a regeneration device. The reaction device comprises a reactor and a disengager, and the disengager is located at an upper part of the reactor. The reactor comprises a tapering section, and diameters of cross sections of the tapering section gradually decrease from bottom to top. Secondary conversion of alkenes caused by back-mixing is reduced, and thus the yield and selectivity to alkenes are increased.

Abstract: A reaction-regeneration device for catalytic dehydrogenation or/and catalytic cracking of alkanes comprises a reaction device and a regeneration device. The reaction device comprises a reactor and a disengager, and the disengager is located at an upper part of the reactor. The reactor comprises a tapering section, and diameters of cross sections of the tapering section gradually decrease from bottom to top. Secondary conversion of alkenes caused by back-mixing is reduced, and thus the yield and selectivity to alkenes are increased.

Abstract: A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases below a reference current level.

Abstract: A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases below a reference current level.

Abstract: A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases below a reference current level.

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

Abstract: Techniques for programming a non-volatile memory device, such as a Flash memory, include floating source lines of memory cells based on a data pattern that is being programmed to the memory device. The source lines to float are selected such that a distance between drain bit lines and source bit lines of different memory cells in a row is maximized. In this manner, leakage current between these drain bit lines and source bit lines can be decreased.

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

Abstract: A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.