Abstract: Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.

Abstract: A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.

Abstract: Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract: A simultaneous operation flash memory capable of providing double protection to An OTP sector. The preferred simultaneous operation flash memory comprises an OTP write-protect CAM, which is in a programmed state if the OTP sector is write-protected. In addition, the preferred simultaneous flash memory further includes an OTP sector lock CAM that is electrically connected with the OTP write-protect CAM. The OTP sector lock CAM is used to lock the OTP write-protect CAM in the programmed state, which, in turn, will designate the OTP sector as read only.

Abstract: A method and apparatus ensure equal address transition detection (ATD) pulse width for all address and chip enable transitions. Address buffer signals from one end of an integrated circuit are combined to form a first combined signal. Address buffer signals and a chip enable signal from a second end of the integrated circuit are combined to form a second combined signal. The two combined signals are logically combined to form a first edge of an ATD pulse. A feedback signal controls the second edge of the ATD pulse for all input signal transitions.

Abstract: The present invention discloses sector-based redundancy that is capable of making repairs using a plurality of redundant columns of memory cells in a dual bank memory device during simultaneous operation. The simultaneous operation memory device includes a plurality of redundant blocks that can be configured to be located in an upper bank or a sliding lower bank. The redundant blocks are comprised of sectors and each sector contains columns of memory cells. During simultaneous operation, the memory device is capable of reading the columns of memory cells in one bank and writing columns of memory cells in the other bank at the same time. In addition, the simultaneous operation memory device uses sector-based redundancy to repair columns of memory cells that are defective in one bank by electrically exchanging them with redundant columns of memory cells and, at the same time, repair columns of memory cells that are defective in the other bank.

Abstract: A memory integrated circuit (100) includes a core cell array (102) having a plurality of core cells for storing data in one of a plurality of states, a plurality of power supply buses (140, 142, 144, 146) including a sensing power supply bus (144) and a sensing ground bus (146) dedicated to sensing states of core cells. The integrated circuit firther includes a sense threshold generating circuit (126) which generates a sense threshold signal in response to a power supply potential on the sensing power supply bus and a ground potential of the sensing ground bus. The integrated circuit still further includes a plurality of sense amplifiers (108) which detect the states of core cells in relation to the sense threshold signal. The sense amplifiers are coupled to the sensing power supply bus and the sensing ground bus so that substantially all power supply noise at the plurality of sense amplifiers and the sense threshold generator is common node noise.

Abstract: A simultaneous operation flash memory capable of write protecting predetermined sectors in the simultaneous operation flash memory. The preferred simultaneous operation flash memory includes a plurality of sectors divided into an upper bank and a sliding lower bank. Each bank is associated with a predetermined amount of sectors in the simultaneous operation flash memory. The simultaneous operation flash memory also includes at least one upper address decoder circuit that has a upper sector select line. During operation, each upper address decoder circuit generates a predetermined output signal on the upper sector select line when selected. In addition, the simultaneous operation flash memory includes at least one lower address decoder circuit including a lower address sector select line, wherein each upper address decoder circuit generates a predetermined output signal on the lower sector select line when selected during operation.