Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

Abstract: A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attractor species having at least one trap site and a chemical affinity for the diffusive species. The diffusive species is transferred from the precursor magnetic material to the precursor trap material where it bonds to the at least one attractor species at the trap sites. The species of the enriched trap material may intermix such that the enriched trap material becomes or stays amorphous. The depleted magnetic material may then be crystallized through propagation from a neighboring crystalline material without interference from the amorphous, enriched trap material. This enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.

Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

Abstract: An apparatus including an array of memory cells comprising transistors is disclosed. One or more of the transistors comprise a crystalline material extending substantially transverse to a base material. A gate dielectric material is adjacent to the crystalline material. A two-dimensional material of a channel region directly intervenes between the gate dielectric material and the crystalline material. The gate dielectric material overlies additional portions of the two-dimensional material of the channel region. One or more gates are adjacent to the gate dielectric material. An electronic device is also disclosed comprising one or more of the transistors. The one or more of the transistors comprise a channel region, a gate dielectric region adjacent to the channel region, and one or more gates adjacent to the gate dielectric region. The channel region comprises opposing sidewalls separated by a pillar structure and substantially perpendicular to a base material.

Abstract: Some embodiments include a construction having a horizontally-extending layer of fluorocarbon material over a semiconductor construction. Some embodiments include methods of filling openings that extend into a semiconductor construction. The methods may include, for example, printing the material into the openings or pressing the material into the openings. The construction may be treated so that surfaces within the openings adhere the material provided within the openings while surfaces external of the openings do not adhere the material. In some embodiments, the surfaces external of the openings are treated to reduce adhesion of the material.

Abstract: A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attractor species having at least one trap site and a chemical affinity for the diffusive species. The diffusive species is transferred from the precursor magnetic material to the precursor trap material where it bonds to the at least one attractor species at the trap sites. The species of the enriched trap material may intermix such that the enriched trap material becomes or stays amorphous. The depleted magnetic material may then be crystallized through propagation from a neighboring crystalline material without interference from the amorphous, enriched trap material. This enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.

Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Some embodiments include a construction having a horizontally-extending layer of fluorocarbon material over a semiconductor construction. Some embodiments include methods of filling openings that extend into a semiconductor construction. The methods may include, for example, printing the material into the openings or pressing the material into the openings. The construction may be treated so that surfaces within the openings adhere the material provided within the openings while surfaces external of the openings do not adhere the material. In some embodiments, the surfaces external of the openings are treated to reduce adhesion of the material.

Abstract: A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

Abstract: Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.

Abstract: A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.