Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: Methods, systems, and devices for enabling fast pulse operation are described. A threshold voltage of a selection component and a requisite duration for a voltage applied to a selection component to reach a threshold voltage in response to a voltage generated by an external source may be determined. The threshold voltage may correspond to a voltage at which the selection component is configured to release electric charge. A voltage may then be generated and applied to an access line that is in electronic communication with the selection component and a memory cell for at least the requisite duration. Electric charge may be stored at the selection component during the requisite duration and transferred to memory cell after the requisite duration.

Abstract: A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.

Abstract: Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than 2 electron-volts. Some embodiments include a memory array having digit lines extending along a vertical direction and wordlines extending along a horizontal direction. The memory array includes memory cells, with each of the memory cells being uniquely addressed by combination of one of the digit lines and one of the wordlines. Each of the memory cells includes a transistor which has GaP channel material. Each of the transistors has first and second source/drain regions spaced from one another by the GaP channel material. The first source/drain regions are coupled with the digit lines, and each of the memory cells includes a capacitor coupled with the second source/drain region of the associated transistor. Other embodiments are disclosed.

Abstract: A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

Abstract: A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

Abstract: Some embodiments include an integrated assembly which has a semiconductor material with a surface. A first layer is over and directly against the surface. The first layer includes oxygen and a first metal. The relative amount of oxygen to the first metal is less than or equal to an amount sufficient to form stoichiometric metal oxide throughout the first layer. A second metal is over and directly against the first layer. A second layer is over and directly against the second metal. The second layer includes nitrogen and a third metal. Some embodiments include an integrated assembly which has a semiconductor material with a surface. A metal is adjacent the surface and is spaced from the surface by a distance of less than or equal to about 10 ?. There is no metal germanide or metal silicide between the metal and the surface.

Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

Abstract: A method of forming a structure comprises forming a pattern of elongate features extending vertically from a base structure. Conductive material is formed on the elongate features. After completing the forming of the pattern of elongate features, the elongate features, the conductive material, or both is (are) exposed to at least one surface treatment gas. The at least one surface treatment gas comprises at least one species formulated to diminish attractive or cohesive forces at a surface of the conductive material. Apparatus and additional methods are also described.

Abstract: Some embodiments include a construction having a horizontally-extending layer of fluorocarbon material over a semiconductor construction. Some embodiments include methods of filling openings that extend into a semiconductor construction. The methods may include, for example, printing the material into the openings or pressing the material into the openings. The construction may be treated so that surfaces within the openings adhere the material provided within the openings while surfaces external of the openings do not adhere the material. In some embodiments, the surfaces external of the openings are treated to reduce adhesion of the material.

Abstract: Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than 2 electron-volts. Some embodiments include a memory array having digit lines extending along a vertical direction and wordlines extending along a horizontal direction. The memory array includes memory cells, with each of the memory cells being uniquely addressed by combination of one of the digit lines and one of the wordlines. Each of the memory cells includes a transistor which has GaP channel material. Each of the transistors has first and second source/drain regions spaced from one another by the GaP channel material. The first source/drain regions are coupled with the digit lines, and each of the memory cells includes a capacitor coupled with the second source/drain region of the associated transistor. Other embodiments are disclosed.

Abstract: In an example, a method may include closing an opening in a structure with a sacrificial material at a first processing tool, moving the structure from the first processing tool to a second processing tool while the opening is closed, and removing the sacrificial material at the second processing tool. The structure may be used in semiconductor devices, such as memory devices.

Abstract: A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.