Abstract: Apparatus having titanium silicide and titanium formed by chemical vapor deposition (CVD) in a contact. The chemical vapor deposition includes forming titanium silicide and/or titanium by combining a titanium precursor in the presence of hydrogen, H2. The chemical vapor deposition may further include forming titanium silicide and/or titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. The chemical vapor deposition may further include forming titanium silicide and/or by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen. For production of titanium silicide, reaction of the titanium precursor may occur with a silicon precursor or a silicon source occurring as part of the contact. Use of a silicon precursor reduces depletion of a silicon base layer in the contact.

Abstract: The present invention is an endpoint detector and a method for quickly and accurately measuring the change in thickness of a wafer in chemical-mechanical polishing processes. The endpoint detector has a reference platform, a measuring face, and a distance measuring device. The reference platform is positioned proximate to the wafer carrier, and the reference platform and measuring device are positioned apart from one another by a known, constant distance. The measuring face is fixedly positioned with respect to the wafer carrier at a location that allows the measuring device to engage the measuring face when the wafer is positioned on the reference platform. Each time the measuring device engages the measuring surface, it measures the displacement of the measuring face with respect to the measuring device. The displacement of the measuring face is proportional to the change in thickness of the wafer between measurements.

Abstract: A method and apparatus for enhanced capacitance per unit area electrodes is utilized in semiconductor memory devices. The capacitance is enhanced by roughening the surface of the bottom electrode in such devices. In one embodiment of the invention, surface roughness is achieved on a polysilicon bottom capacitor electrode by depositing doped polysilicon on the outside surfaces of a bottom capacitor electrode and vacuum annealing. In another embodiment of the invention, surface roughness is achieved by depositing a GeO2-embedded GeBPSG layer on a substrate, annealing, selectively etching to remove GeO2, forming a container, and depositing a blanket rough polysilicon layer over the GeBPSG layer to replicate the underlying surface roughness.

Abstract: A method and apparatus for detecting the endpoint of CMP processing on semiconductor wafer in which a lower layer of material with a first reflectivity is positioned under an upper layer of material with a second reflectivity. Initially an endpoint site is selected on the wafer in a critical area where a boundary between the upper and lower layers defines the desired endpoint of the CMP process. The critical area on the wafer is generally determined by analyzing in the circuit design and the polishing characteristics of previously polished test wafers to denote the last points on the wafer from which the upper layer is desirably removed by CMP processing. After an endpoint site is selected, a light beam impinges the polished surface of the wafer and reflects off of the surface of the wafer to a photo-sensor. The photosensor senses the actual intensity of the reflected light beam.

Abstract: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.

Abstract: A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.

Abstract: An integrated circuit includes a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle.

Abstract: A method for forming a capacitor (36) outwardly from a semiconductor substrate (10). Alternating layers of first and second materials (20 and 22) are formed outwardly from a semiconductor substrate. A first set of vias (24) is formed through the layers of first and second materials (20 and 22) to the semiconductor substrate(10). A second set of vias (26) is formed through the layers of first and second materials (20 and 22). Each via in the second set (26) is formed in a location that is adjacent to one of the vias of the first set (24). A trunk (28) of the first plate (34) of the capacitor (36) is formed by selectively depositing a semiconductor material, such as poly-silicon, to fill the first set of vias (24). A set of fins (30) and a dome (32) are formed on the trunk (28) to complete the first plate (34) by removing the alternating layers of first layers (20) and selectively depositing a semiconductor material between the second layers (22).

Abstract: A method and apparatus for enhanced capacitance per unit area electrodes is utilized in semiconductor memory devices. The capacitance is enhanced by roughening the surface of the bottom electrode in such devices. In one embodiment of the invention, surface roughness is achieved on a polysilicon bottom capacitor electrode by depositing doped polysilicon on the outside surfaces of a bottom capacitor electrode and vacuum annealing. In another embodiment of the invention, surface roughness is achieved by depositing a GeO.sub.2 -embedded GeBPSG layer on a substrate, annealing, selectively etching to remove GeO.sub.2, forming a container, and depositing a blanket rough polysilicon layer over the GeBPSG layer to replicate the underlying surface roughness.

Abstract: A method and apparatus for detecting the endpoint of CMP processing on semiconductor wafer in which a lower layer of material with a first reflectivity is positioned under an upper layer of material with a second reflectivity. Initially an endpoint site is selected on the wafer in a critical area where a boundary between the upper and lower layers defines the desired endpoint of the CMP process. The critical area on the wafer is generally determined by analyzing in the circuit design and the polishing characteristics of previously polished test wafers to denote the last points on the wafer from which the upper layer is desirably removed by CMP processing. After an endpoint site is selected, a light beam impinges the polished surface of the wafer and reflects off of the surface of the wafer to a photo-sensor. The photosensor senses the actual intensity of the reflected light beam.

Abstract: A slurry composition enhances the removal of polish-resistant surface moieties from the surface of a semiconductor wafer during chemical-mechanical polishing. The slurry composition is a mixture including a solvent, a plurality of abrasive particles, and a chelating agent. The abrasive particles abrade the surface of the wafer to remove surface moieties and underlying material. The chelating agent is selected to react with polish-resistant surface moieties on the surface of the wafer surface, to thereby render the surface moieties easier to remove from the surface layer with substantially non-aggressive chemical-mechanical polishing techniques. In operation, the surface moieties and the underlying bulk material are removed by a combination of the chemical effects of the chelating agent and the mechanical effects of the abrasive particles.

Abstract: In a semiconductor fabrication method for forming a transistor structure upon a semiconductor substrate, a nitride layer is also formed over the semiconductor substrate. A gate oxide layer is formed over a region of the semiconductor substrate. The gate oxide layer has a relatively thinner oxide region over the nitride layer and a relatively thicker oxide region over the substrate adjacent the nitride layer. A transistor gate is formed extending over the relatively thinner oxide region and over the relatively thicker oxide region. The transistor thus formed is therefore asymmetric. A first transistor active region is formed in the vicinity of the relatively thicker oxide region and a second transistor active region is formed in the vicinity of the relatively thinner oxide region. The nitride layer can be formed by rapid thermal nitridization of the semiconductor substrate. The relatively thinner oxide region can be one-half as thick as the relatively thinner oxide region.

Abstract: In a method for fabricating an integrated circuit interconnect upon a semiconductor substrate an integrated circuit component is formed upon the surface of the semiconductor substrate. A copper interconnect is formed and electrically coupled to the integrated circuit component. A metal is introduced in the copper interconnect to provide an introduced metal. A gas is reacted with the implanted metal to form a barrier layer cladding upon the copper interconnect. The metal is introduced substantially near the surface of the copper interconnect and substantially all of the introduced metal diffuses to the surface and reacts with the gas. Thus the resistivity of the introduced interconnect is substantially equal to the resistivity of copper. The metal can be, for example, titanium, tantalum, chromium, aluminium or tungsten. The gas can contain, for example, nitrogen, oxygen and carbon.

Abstract: A method and apparatus for selectively conditioning a planarizing surface of a polishing pad. In one embodiment, a conditioning system has a carrier assembly with an arm that may be positioned over a polishing pad, a conditioning element coupled to the arm, and an actuator coupled to the arm to move the conditioning element into engagement with the planarizing surface of the polishing pad. The conditioning element is an abrasive member, such as an abrasive disk or a brush. The conditioning system may also have a controller operatively coupled to the engagement actuator to control an operating parameter of the conditioning element as a function of the distribution of a surface characteristic across the planarizing surface of the polishing pad.

Abstract: A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

Abstract: In a semiconductor fabrication method for forming a transistor structure upon a semiconductor substrate, a nitride layer is also formed over the semiconductor substrate. A gate oxide layer is formed over a region of the semiconductor substrate. The gate oxide layer has a relatively thinner oxide region over the nitride layer and a relatively thicker oxide region over the substrate adjacent the nitride layer. A transistor gate is formed extending over the relatively thinner oxide region and over the relatively thicker oxide region. The transistor thus formed is therefore asymmetric. A first transistor active region is formed in the vicinity of the relatively thicker oxide region and a second transistor active region is formed in the vicinity of the relatively thinner oxide region. The nitride layer can be formed by rapid thermal nitridization of the semiconductor substrate. The relatively thinner oxide region can be one-half as thick as the relatively thinner oxide region.

Abstract: A method of forming a polysilicon electrode having at least one roughened surface is performed by roughening a template layer to form a roughened template layer. A layer of polysilicon is next deposited on top of the roughened template layer. The polysilicon electrode is then formed by etching away the roughened template layer, and thereby exposing a roughened surface on the polysilicon electrode.

Abstract: The present invention is an endpoint detector and a method for quickly and accurately measuring the change in thickness of a wafer in chemical-mechanical polishing processes. The endpoint detector has a reference platform, a measuring face, and a distance measuring device. The reference platform is positioned proximate to the wafer carrier, and the reference platform and measuring device are positioned apart from one another by a known, constant distance. The measuring face is fixedly positioned with respect to the wafer carrier at a location that allows the measuring device to engage the measuring face when the wafer is positioned on the reference platform. Each time the measuring device engages the measuring surface, it measures the displacement of the measuring face with respect to the measuring device. The displacement of the measuring face is proportional to the change in thickness of the wafer between measurements.

Abstract: A method for forming a capacitor (36) outwardly from a semiconductor substrate (10). Alternating layers of first and second materials (20 and 22) are formed outwardly from a semiconductor substrate. A first set of vias (24) is formed through the layers of first and second materials (20 and 22) to the semiconductor substrate(10). A second set of vias (26) is formed through the layers of first and second materials (20 and 22). Each via in the second set (26) is formed in a location that is adjacent to one of the vias of the first set (24). A trunk (28) of the first plate (34) of the capacitor (36) is formed by selectively depositing a semiconductor material, such as poly-silicon, to fill the first set of vias (24). A set of fins (30) and a dome (32) are formed on the trunk (28) to complete the first plate (34) by removing the alternating layers of first layers (20) and selectively depositing a semiconductor material between the second layers (22).