Patents by Inventor Guy F. Hudson

Guy F. Hudson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8053371
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: November 8, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
  • Patent number: 7294570
    Abstract: A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: November 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Richard L. Elliott, Guy F. Hudson
  • Patent number: 7244681
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Renee Zahorik, legal representative, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon, Russell C. Zahorik, deceased
  • Patent number: 7214125
    Abstract: A method and apparatus for processing a microelectronic substrate. In one embodiment, the method can include planarizing the microelectronic substrate with a planarizing liquid and rinsing the substrate with a rinsing liquid having a pH approximately the same as a pH of the planarizing liquid. The rinsing step can be completed while the substrate remains on a polishing pad of the apparatus, or, alternatively, the substrate can be removed to a rinsing chamber for rinsing. In another embodiment, the method can include conditioning the polishing pad by removing polishing pad material from the polishing pad and then cleaning the microelectronic substrate by engaging the substrate with the same polishing pad and moving at least one of the polishing pad and the substrate relative to the other of the polishing pad and the substrate after conditioning the polishing pad.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Judson R. Sharples, Kenneth F. Zacharias, Guy F. Hudson
  • Patent number: 7122475
    Abstract: A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical planarization processes. In one aspect of the invention, a bi-modal slurry is fabricated by removing a first type of selected abrasive particles from a first abrasive particle solution to form a treated flow of the first solution. The treated flow of the first solution is then combined with a flow of a second solution having a plurality of second abrasive particles. The abrasive particles of the first type are accordingly removed from the first solution separately from the second solution such that the second abrasive particles in the second solution do not affect the removal of the abrasive particles of the first type from the first solution. In another aspect of the invention, a second type of selected abrasive particles are removed from the second solution prior to mixing with the first solution.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: October 17, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Guy F. Hudson
  • Patent number: 7045017
    Abstract: The inventive method cleans residual titanium accumulations and other undesirable materials from a planarized surface of a wafer to produce a planarized surface with less than about fifty defects per wafer. After a metallic layer of material has been planarized using a CMP process, loose residual particles of undesirable material are removed from the planarized surface. The residual titanium accumulations remaining on the planarized surface are then detached from the planarized surface, which produces additional, new particles on the surface of the wafer. The additional particles produced by the detaching step are then scrubbed from the planarized surface until the planarized surface has less than approximately 50 defects per wafer.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: May 16, 2006
    Assignee: Micron Technology, Inc.
    Inventors: David Gonzales, Guy F. Hudson
  • Patent number: 6913523
    Abstract: A method and apparatus for processing a microelectronic substrate. In one embodiment, the method can include planarizing the microelectronic substrate with a planarizing liquid and rinsing the substrate with a rinsing liquid having a pH approximately the same as a pH of the planarizing liquid. The rinsing step can be completed while the substrate remains on a polishing pad of the apparatus, or, alternatively, the substrate can be removed to a rinsing chamber for rinsing. In another embodiment, the method can include conditioning the polishing pad by removing polishing pad material from the polishing pad and then cleaning the microelectronic substrate by engaging the substrate with the same polishing pad and moving at least one of the polishing pad and the substrate relative to the other of the polishing pad and the substrate after conditioning the polishing pad.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: July 5, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Judson R. Sharples, Kenneth F. Zacharias, Guy F. Hudson
  • Patent number: 6889698
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: May 10, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
  • Publication number: 20040229551
    Abstract: A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical planarization processes. In one aspect of the invention, a bi-modal slurry is fabricated by removing a first type of selected abrasive particles from a first abrasive particle solution to form a treated flow of the first solution. The treated flow of the first solution is then combined with a flow of a second solution having a plurality of second abrasive particles. The abrasive particles of the first type are accordingly removed from the first solution separately from the second solution such that the second abrasive particles in the second solution do not affect the removal of the abrasive particles of the first type from the first solution. In another aspect of the invention, a second type of selected abrasive particles are removed from the second solution prior to mixing with the first solution.
    Type: Application
    Filed: April 1, 2004
    Publication date: November 18, 2004
    Inventor: Guy F. Hudson
  • Patent number: 6803316
    Abstract: Methods of oxidizing the surface of a photoresist material on a semiconductor substrate to alter the photoresist material surface to be substantially hydrophilic. Oxidation of the photoresist material surface substantially reduces or eliminates stiction between a planarizing pad and the photoresist material surface during chemical mechanical planarization. This oxidation of the photoresist material may be achieved by oxygen plasma etching or ashing, by immersing the semiconducter substrate in bath containing an oxidizing agent, or by the addition of an oxidizing agent to the chemical slurry used during planarization of the resist material.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: October 12, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Guy F. Hudson, Michael A. Walker
  • Publication number: 20040198195
    Abstract: A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical planarization processes. In one aspect of the invention, a bi-modal slurry is fabricated by removing a first type of selected abrasive particles from a first abrasive particle solution to form a treated flow of the first solution. The treated flow of the first solution is then combined with a flow of a second solution having a plurality of second abrasive particles. The abrasive particles of the first type are accordingly removed from the first solution separately from the second solution such that the second abrasive particles in the second solution do not affect the removal of the abrasive particles of the first type from the first solution. In another aspect of the invention, a second type of selected abrasive particles are removed from the second solution prior to mixing with the first solution.
    Type: Application
    Filed: April 1, 2004
    Publication date: October 7, 2004
    Inventor: Guy F. Hudson
  • Publication number: 20040198194
    Abstract: A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical planarization processes. In one aspect of the invention, a bi-modal slurry is fabricated by removing a first type of selected abrasive particles from a first abrasive particle solution to form a treated flow of the first solution. The treated flow of the first solution is then combined with a flow of a second solution having a plurality of second abrasive particles. The abrasive particles of the first type are accordingly removed from the first solution separately from the second solution such that the second abrasive particles in the second solution do not affect the removal of the abrasive particles of the first type from the first solution. In another aspect of the invention, a second type of selected abrasive particles are removed from the second solution prior to mixing with the first solution.
    Type: Application
    Filed: April 1, 2004
    Publication date: October 7, 2004
    Inventor: Guy F. Hudson
  • Publication number: 20040192174
    Abstract: A method and apparatus for processing a microelectronic substrate. In one embodiment, the method can include planarizing the microelectronic substrate with a planarizing liquid and rinsing the substrate with a rinsing liquid having a pH approximately the same as a pH of the planarizing liquid. The rinsing step can be completed while the substrate remains on a polishing pad of the apparatus, or, alternatively, the substrate can be removed to a rinsing chamber for rinsing. In another embodiment, the method can include conditioning the polishing pad by removing polishing pad material from the polishing pad and then cleaning the microelectronic substrate by engaging the substrate with the same polishing pad and moving at least one of the polishing pad and the substrate relative to the other of the polishing pad and the substrate after conditioning the polishing pad.
    Type: Application
    Filed: March 22, 2004
    Publication date: September 30, 2004
    Inventors: Judson R. Sharples, Kenneth F. Zacharias, Guy F. Hudson
  • Patent number: 6794289
    Abstract: A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical planarization processes. In one aspect of the invention, a bi-modal slurry is fabricated by removing a first type of selected abrasive particles from a first abrasive particle solution to form a treated flow of the first solution. The treated flow of the first solution is then combined with a flow of a second solution having a plurality of second abrasive particles. The abrasive particles of the first type are accordingly removed from the first solution separately from the second solution such that the second abrasive particles in the second solution do not affect the removal of the abrasive particles of the first type from the first solution. In another aspect of the invention, a second type of selected abrasive particles are removed from the second solution prior to mixing with the first solution.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: September 21, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Guy F. Hudson
  • Publication number: 20040180535
    Abstract: A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 16, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Richard L. Elliott, Guy F. Hudson
  • Publication number: 20040089326
    Abstract: The inventive method cleans residual titanium accumulations and other undesirable materials from a planarized surface of a wafer to produce a planarized surface with less than about fifty defects per wafer. After a metallic layer of material has been planarized using a CMP process, loose residual particles of undesirable material are removed from the planarized surface. The residual titanium accumulations remaining on the planarized surface are then detached from the planarized surface, which produces additional, new particles on the surface of the wafer. The additional particles produced by the detaching step are then scrubbed from the planarized surface until the planarized surface has less than approximately 50 defects per wafer.
    Type: Application
    Filed: November 4, 2003
    Publication date: May 13, 2004
    Inventors: David Gonzales, Guy F. Hudson
  • Patent number: 6716089
    Abstract: A method and apparatus for processing a microelectronic substrate. In one embodiment, the method can include planarizing the microelectronic substrate with a planarizing liquid and rinsing the substrate with a rinsing liquid having a pH approximately the same as a pH of the planarizing liquid. The rinsing step can be completed while the substrate remains on a polishing pad of the apparatus, or, alternatively, the substrate can be removed to a rinsing chamber for rinsing. In another embodiment, the method can include conditioning the polishing pad by removing polishing pad material from the polishing pad and then cleaning the microelectronic substrate by engaging the substrate with the same polishing pad and moving at least one of the polishing pad and the substrate relative to the other of the polishing pad and the substrate after conditioning the polishing pad.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: April 6, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Judson R. Sharples, Kenneth F. Zacharias, Guy F. Hudson
  • Patent number: 6713384
    Abstract: A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: March 30, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Richard L. Elliott, Guy F. Hudson
  • Publication number: 20040038543
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Application
    Filed: August 25, 2003
    Publication date: February 26, 2004
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon, Renee Zahorik
  • Patent number: RE39413
    Abstract: The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low friction material positioned over the substrate, and an upper layer deposited on the low friction material stratum. The low friction stratum has a polish-stop surface positioned at a level substantially proximate to a desired endpoint of the chemical-mechanical planarization process. The upper layer, which is made from either a conductive material or an insulative material, has a higher polishing rate than that of the low friction stratum. In operation, the low friction stratum resists chemical-mechanical planarization with either hard or soft polishing pads to stop the planarization process at the desired endpoint.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: November 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Guy F. Hudson, Renee Zahorik, Russell C. Zahorik