Abstract: A floating point flag combining or accumulating circuit includes an analysis circuit that receives a plurality of floating point operands, each having encoded status flag information, and a result assembler. The analysis circuit analyzes the plurality of floating point operands and provides an indication of one or more predetermined formats in which the plurality of floating point operands are represented. The result assembler receives the indication from the analysis circuit and assembles an accumulated result that represents a value and combines the encoded status flag information from at least two of the plurality of floating point operands.

Abstract: A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the square root of the first floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: A set of structures and techniques are described herein whereby an exemplary concurrent shared object, namely a shared skip list, can be implemented in a lock-free manner. Indeed, we have developed a number of interesting variants of a lock-free shared skip-list, including variants that may be employed to provide a lock-free shared dictionary. In some variants, a key-value dictionary is implemented.

Abstract: A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one embodiment, a floating point operand data structure includes a first portion having floating point operand data and a second portion having embedded status information associated with at least one status condition of the operand data. The status condition may be determined from only the embedded status information. The status condition may also be associated with at least one floating point operation that generated the operand data structure. The outcome of a conditional floating point instruction may be based on the embedded status information without regard to contents of the floating point status register.

Abstract: A system for providing a floating point sum includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data with the second floating point operand respectively. In addition, the system includes a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the sum of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: A system for providing floating point division includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system includes a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the result of the division of the first floating point operand by the second floating point operand. Additionally, the results circuit provides resulting status embedded within the resulting floating point operand.

Abstract: Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and a first input interval lower-point. Next, computing an output interval includes producing a second result from the conditional selection, the operands respectively including a second input interval upper-point, the first input interval upper-point, and the first input interval lower-point. Furthermore, computing an output interval includes producing a third result from a conditional division using the first operand, the second operand, and the third operand, the operands respectively including the first result, the second input interval upper-point, and the second input interval lower-point.

Abstract: A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal,

Abstract: Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Then a third product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Next a fourth product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. And finally, the output interval is produced including an output interval lower-point and an output interval upper-point, the output interval lower-point being the minimum of the first product and the third product, and the output interval upper-point being the maximum of the second product and the fourth product.

Abstract: A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group including: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact.

Abstract: A system and method for adding routing information for a node to a routing table, which efficiently makes necessary changes to the routing table to support routing to and from the node, while maintaining the deadlock-free quality of the paths described by the routing table. The routing table is generated by storing routing information in the routing table that reflects and describes a deadlock-free set of paths through a network of nodes. A row of entries is added to the routing table describing how to forward data units from the node. A column of entries is added to the routing table describing how to forward data units addressed to the node. The forwarding information within each entry added to the routing table maintains the deadlock-free quality of the set of paths represented by the forwarding table.

Abstract: A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction.

Abstract: A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a separate floating point status register for the inexact status information. In one embodiment, inexact status information is preserved by determining whether the at least one operand is inexact. Further, an intermediate result of the floating point computation is analyzed to determine whether it is inexact. Finally, the intermediate result is rounded based on whether the at least one operand is inexact and whether the intermediate result is inexact to preserve an inexact status of the at least one operand and the intermediate result.

Abstract: Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention provides a method of enhancing support of an interval computation when performing a floating point arithmetic operation, comprising the steps, performed by a processor, of receiving a first floating point operand, receiving a second floating point operand, executing the floating point arithmetic operation on the first floating point operand and the second floating point operand, determining whether a NaN substitution is necessary, producing a floating point result if the NaN substitution is determined to be unnecessary, and substituting an alternative value as the floating point result if the NaN substitution is determined to be necessary.

Abstract: A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may supply the operand to the analysis circuit. The result generator circuit is responsive to at least one control signal and asserts a result signal if the floating point analysis circuit matches the floating point status to a predetermined format specified by the control signal. The result signal can condition the outcome of a floating point instruction. The result generator may also respond to multiple control signals asserted when testing a single operand for different formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, exact, and inexact.

Abstract: The Hat Trick deque requires only a single DCAS for most pushes and pops. The left and right ends do not interfere with each other until there is one or fewer items in the queue, and then a DCAS adjudicates between competing pops. By choosing a granularity greater than a single node, the user can amortize the costs of adding additional storage over multiple push (and pop) operations that employ the added storage. A suitable removal strategy can provide similar amortization advantages. The technique of leaving spare nodes linked in the structure allows an indefinite number of pushes and pops at a given deque end to proceed without the need to invoke memory allocation or reclamation so long as the difference between the number of pushes and the number of pops remains within given bounds. Both garbage collection dependent and explicit reclamation implementations are described.

Abstract: A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.

Abstract: A linked-list-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the linked-list-based algorithm allows non-blocking completion of access operations without restricting concurrency in accessing the deque's two ends. The new implementation is based at least in part on a new technique for splitting a pop operation into two steps, marking that a node is about to be deleted, and then deleting it. Once marked, the node logically deleted, and the actual deletion from the list can be deferred. In one realization, actual deletion is performed as part of a next push or pop operation performed at the corresponding end of the deque.

Abstract: We present a methodology for transforming concurrent data structure implementations that depend on garbage collection to equivalent implementations that do not. Assuming the existence of garbage collection makes it easier to design implementations of concurrent data structures, particularly because it eliminates the well-known ABA problem. However, this assumption limits their applicability. Our results demonstrate that, for a significant class of data structures, designers can first tackle the easier problem of an implementation that does depend on garbage collection, and then apply our methodology to achieve a garbage-collection-independent implementation. Our methodology is based on the well-known reference counting technique, and employs the double compare-and-swap operation.

Abstract: An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent floating point unit groups the plurality of operands into at least one group, determines a plurality of scale factors for the plurality of operands, respectively, and provides a running sum of the plurality of scale factors. The extended exponent floating point unit further scales the plurality of operands to obtain a plurality of scaled operands, multiplies the plurality of scaled operands to obtain a group product, and scales the group product to obtain a scaled group product. The scaled group product is adjusted based on the running sum. The plurality of operands are grouped such that when all the plurality of scaled operands in the at least one group are multiplied an overflow or underflow will not occur.