Abstract: A system and method for calculating a deadlock-free free set of paths in a network generates an ordered set of deadlock-free sub-topologies, referred to as “layers.” The ordered set of layers is then used to determine a deadlock-free set of paths through the network by performing a shortest-path route calculation with the following constraint: starting at any given layer, for each node, proceed to calculate a shortest path to every other node in the graph where, at any node being utilized to assess a given minimum path, the path may move to any higher-ordered layer, but may not return to a lower-ordered layer.

Abstract: A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the determined format is an infinity format or an overflow format. The exponent field bits and the fraction field bits of the result are set to corresponding exponent field bits and corresponding fraction field bits of the floating point operand if the determined format is a not-a-number (NaN) format. At least one of the fraction field bits of the result is adaptively cleared if the determined format is a denormalized format or a delimited format.

Abstract: A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined formats in which the plurality of operands are represented, and generates one or more control signals. The result assembler receives the control signals from the circuit, along with one or more inputs, and assembles a result.

Abstract: A logarithm unit computes an integer part of a logarithm of a floating point operand according to an embodiment of the present invention. The logarithm unit analyzes a format of the floating point operand and generates at least one signal representative of the format. The logarithm unit determines a magnitude of an unbiased exponent of the floating point operand as an intermediate result based on the at least one signal, wherein the unbiased exponent is represented by unbiased exponent bits. Still further, the logarithm unit determines an exponent field and a fraction field high part of the intermediate result.

Abstract: A sequentially performed implementation of a compound compare-and-swap (nCAS) operation has been developed. In one implementation, a double compare-and-swap (DCAS) operation does not result in a fault, interrupt, or trap in the situation where memory address A2 is invalid and the contents of memory address A1 are unequal to C1. In some realizations, memory locations addressed by a sequentially performed nCAS or DCAS instruction are reserved (e.g., locked) in a predefined order in accordance with a fixed total order of memory locations. In this way, deadlock between concurrently executed instances of sequentially performed nCAS instructions can be avoided. Other realizations defer responsibility for deadlock avoidance to the programmer.

Abstract: A novel linked-list-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, non-blocking completion of access operations is achieved without restricting concurrency in accessing the deque's two ends. In various realizations in accordance with the present invention, the set of values that may be pushed onto a shared object is not constrained by use of distinguishing values. In addition, an explicit reclamation embodiment facilitates use in environments or applications where automatic reclamation of storage is unavailable or impractical.

Abstract: In accordance with methods and systems consistent with the present invention, an improved failure recovery system is provided that, upon detecting a failure, generates new routings for the network which (1) avoid the failure and (2) avoid deadlock. In this manner, after a failure is detected, the network remains as operational as possible while still avoiding deadlock. Thus, by using the improved failure recovery system, a network failure has a much less severe impact on the network than in conventional systems.

Abstract: A system is disclosed for providing, from an input data word comprising a plurality of input data units having an input arrangement and a mask word comprising a plurality of mask bits each associated with one of the data units, an output data word in which the data units are arranged according to the mask bits. The system includes a bit balancer module and a plurality of rearrangement modules. The bit balancer module is configured to divide the input data units comprising the input data word into a plurality of data word portions, each data unit being assigned to one of the data word portions based on a pattern of mask bits of the mask word relative to the mask bit associated with the respective data unit. Each rearrangement module is configured to provide, from one of the data word portions and associated mask bits, an output data word portion in which the data units are arranged according to the mask bits.

Abstract: A system is described for rearranging data units of a data word in accordance with a mask word, the mask word having a plurality of mask bits each associated with a data unit, each mask bit having one of a set condition or a clear condition. The system includes a control module and a shifter module. The control module is configured to generate, for each mask bit, values identifying the number of mask bits to the left of the respective mask bit which have one of the set condition or the clear condition and the number of mask bits to the right of the respective mask bit which have the other of the set condition or the clear condition. The shifter module is configured to shift data units of the data word in accordance with the values generated by the control module.

Abstract: Methods and systems consistent with the present invention provide a family of networks ranging from 2 nodes to 16 nodes that can be partitioned in an unconstrained manner. That is, where the number of nodes in one of these networks is N, subnetwork can contain any number of nodes from 1 to N−1 as long as the total number of nodes in both subnetworks equals N. Furthermore, each subnetwork can be partitioned repeatedly until reaching the atomic level (i.e., when the subnetwork contains a single node). In accordance with methods and systems consistent with the present invention, when a network is partitioned, each subnetwork has various desirable properties. For example, the maximum path length between any two nodes in each subnetwork nodes is 3, and each to subnetwork has a set of deadlock-free routings.

Abstract: A system is described for rearranging an input data word in relation to a mask word, the data word comprising a plurality of input data units in a series of input data unit positions, each associated with a respective one of a plurality of bits of the mask word in a series of mask bit positions, each mask bit having one of a plurality of conditions, to provide an output data word comprising a plurality of output data units in a series of output data unit positions. The system comprises a control module and a shift module. The control module is configured to identify, for each output data unit position, the number of bits in bit positions in the mask word to one end of that bit position which have one of the conditions, and the number of bits in bit positions to another end of the mask word have another of the conditions.

Abstract: A functional unit is described for selectively performing a number of types of bit rearrangement operations, including a generalized bit reverse operation and a generalized shuffle/unshuffle operation, and in addition left and right unsigned shift operations and an arithmetic shift right operation. The functional unit includes a shifter array and a control signal generator. The shifter array includes a plurality of selector circuits arrayed in a number of stages for shifting bits of an input data word in accordance with control signals, the output of the last stage corresponding to a rearranged output data word. The control signal generator generates control signals in response to rearrangement operation type and pattern information.

Abstract: A system is disclosed for rearranging data units of a data word in accordance with a mask word, the mask word having a plurality of mask bits each associated with a data unit, each mask bit having one of a set condition and a clear condition. The system includes an array of interconnected swap modules organized in a series of swap stages, each swap module having two inputs and two outputs. Each swap module is configured to receive at each input a data unit and associated mask bits and couple the data units to the respective outputs in relation to the associated mask bit's condition.

Abstract: In accordance with methods and systems consistent with the present invention, an improved technique for reconfiguring networks is provided. By using this technique, a network administrator can reconfigure their network while it remains operational. As a result, users can continue to utilize the network during reconfiguration. Additionally, in accordance with methods and systems consistent with the present invention, a number of network topologies are provided that are designed to facilitate reconfiguration. When using one of these topologies, the network can be reconfigured with a minimal amount of recabling, thus reducing the amount of time required for reconfiguration.

Abstract: In accordance with methods and systems consistent with the present invention, a number of improved network topologies are provided that have been selected to improve network performance based on various performance characteristics. The topologies are also selected to facilitate network reconfiguration, including adding nodes and removing, nodes. As a result, the network topologies in accordance with methods and systems consistent with the present invention do not follow a rigid, predefined pattern; rather, these topologies have been selected for network performance purposes as well as reconfiguration purposes.

Abstract: In accordance with methods and systems consistent with the present invention, an improved deadlock-free routing system is provided to a family of network topologies where both the configuration of the networks and the routings are designed to optimize performance. In this system, each network utilizes static routing tables that perform deadlock-free routing in an optimized manner to reduce the amount of communication overhead when routing traffic. Specifically, the routings in accordance with methods and systems consistent with the present invention require no more than two hops for networks up to a size of 16 nodes. As a result, the deadlock-free routing provided in accordance with methods and systems consistent with the present invention incurs less communications overhead than some conventional systems while still avoiding deadlock.

Abstract: A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines a plurality of formats, including a normalized format and a de-normalized format, using a common floating point representation that defines a unitary normalized format. The system includes a base to common representation converter, a processor and a common to base representation converter. The base to common representation converter converts numbers from the base floating point representation to the common floating point representation, so that all numbers involved in a computatoin will be expressed in the unitary normalized format. The processor is configured to perform a mathematical operation of at least one predetermined type in connection with the converted numbers generated by the base to common representation converter to generate a floating point result in the common representation.

Abstract: A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines a plurality of formats, including a normalized format and a de-normalized format, using a common floating point representation that defines a unitary normalized format. The system includes a base to common representation converter, a processor and a common to base representation converter. The base to common representation converter converts numbers from the base floating point representation to the common floating point representation, so that all numbers involved in a computation will be expressed in the unitary normalized format. The processor is configured to perform a mathematical operation of at least one predetermined type in connection with the converted numbers generated by the base to common representation converter to generate a floating point result in the common representation.

Abstract: A new “partial trap barrier” instruction can be inserted in an instruction stream to cut off trap shadows of instructions of a respective one of a plurality of particular classes associated with each instruction. Several criteria may be used to assign instructions to trap barrier classes, including (i) explicit encoding of a trap barrier value which is contained in the respective instructions; (ii) resource(s) of the processor which is or are used in their execution, and (iii) where the instructions are located in the instruction stream in relation to the partial trap barrier instructions in the instruction stream. When the processor executes a partial trap barrier instruction in a particular class, while an earlier instruction in the same class is casting its trap shadow, the processor will stall the pipeline in connection with an instruction of the same class after the partial trap barrier instruction in the pipeline, as well as instructions in the instruction stream subsequent thereto.

Abstract: A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines a plurality of formats, including a normalized format and a de-normalized format, using a common floating point representation that defines a unitary normalized format. The system includes a base to common representation converter, a processor and a common to base representation converter. The base to common representation converter converts numbers from the base floating point representation to the common floating point representation, so that all numbers involved in a computation will be expressed in the unitary normalized format. The processor is configured to perform a mathematical operation of at least one predetermined type in connection with the converted numbers generated by the base to common representation converter to generate a floating point result in the common representation.