Abstract: A cache is provided comprising a plurality of ways, each way of the plurality of ways comprising a data array, wherein a data item stored by the cache is stored in the data array of one of the plurality of ways. A way tracker of the cache has a plurality of entries, each entry of the plurality of entries for storing a data item identifier and for storing, in association with the data item identifier, an indication of a selected way of the plurality of ways to indicate that a data item identified by the data item identifier is stored in the selected way. Each entry of the way tracker is further for storing a miss indicator in association with the data item identifier, wherein the miss indicator is set by the cache when a lookup for a data item identified by that data item identifier has resulted in a cache miss. A corresponding method of caching data is also provided.

Abstract: A processing apparatus 200 includes floating point arithmetic circuitry 214, 216 coupled to monitoring circuitry 226. The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a minimum exponent value processed when performing the floating point arithmetic operations. The monitoring circuitry may be selectively enabled in dependence upon a virtual machine identifier, an application specific identifier or a program counter value range. Exponent limit data may be gathered in respect of different portions of the floating point arithmetic circuitry and/or may be aggregated to form global exponent limit data for the system.

Abstract: A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words.

Abstract: A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, said memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying said scores by adding said score updates to said scores; and a selector circuit for selecting at least o

Abstract: A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element.

Abstract: A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, the memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying the scores by adding the score updates to the scores; and a selector circuit for selecting at least one n

Abstract: A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, the memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying the scores by adding the score updates to the scores; and a selector circuit for selecting at least one n

Abstract: A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, said memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying said scores by adding said score updates to said scores; and a selector circuit for selecting at least o

Abstract: A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element.

Abstract: A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, said memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying said scores by adding said score updates to said scores; and a selector circuit for selecting at least o

Abstract: A microprocessor system comprising a register bank 6 and an execution unit 8 incorporating a barrel shifter 10 and an ALU 12 is provided. The register bank 6 has X read ports whilst at least some of the program instructions require Y input operands to be read from the register bank 6, where Y is greater than X. A cache register 18 is provided that caches previously read input operands for supply to the barrel shifter 10 and if it is detected that the same register is being read a second or subsequent time then this cached value is supplied to the barrel shifter 10 rather than requiring a further read from the register bank 6. A tag register 20 associated with each cache register 18 draws data indicating from which register within the register bank 6 the cached data value was copied. A valid flag 22 indicates that that cached data value is still current, i.e. at the corresponding register within the register bank 6 has not been overwritten.

Abstract: A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.

Abstract: A data processing system is described utilizes a multiplier-accumulator 108 that performs both a first class of multiply-accumulate instructions and a second class of multiply-accumulate instructions. The first class of multiply-accumulate instructions are of the form N*N+N.fwdarw.N and the second class of multiply-accumulate instructions are of the form N*N+2N.fwdarw.2N. The second class of multiply-accumulate instructions provide a greater precision of arithmetic in a single instruction and avoid the use of excessive instruction set space by being constrained that the result is written back into the two registers from which the 2N-bit accumulate value was taken. The multiplier-accumulator also provides N*N.fwdarw.N and N*N.fwdarw.2N multiplication operations.

Abstract: An iterative multiplier having a multiplier core generating partial results upon each iteration. When an early terminate of a multiply instruction occurs, at least one of the partial results is passed to a general purpose barrel shifter for bit realignment dependent upon the number of iterations performed before the early terminate occurred. The bit realigned partial results are then passed to an arithmetic logic unit where they are added to yield the final result.