Abstract: A semiconductor structure can be created by forming an insulator layer over a surface of a substrate. An intermediate layer can be formed on top of the insulator layer, wherein openings in the intermediate layer may expose regions of the insulator. Openings may be formed in the exposed regions of the insulator layer to create exposed areas of the substrate. A first element of a multi-element semiconductor can be deposited onto the exposed regions of the insulator layer, into the openings in the exposed regions of the insulator layer, and onto the exposed areas of the substrate. A capping layer can be formed over the first element of the multi-element semiconductor. The first element can be melted. A liquid solution can be created by dissolving a second element of the multi-element semiconductor into first element. A multi-element semiconductor, seeded off the substrate, can be formed from the liquid solution.

Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

Abstract: Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.

Abstract: A method for fabricating a III-V nanowire. The method may include providing a semiconductor substrate, which includes an insulator, with a wide-bandgap layer on the top surface of the semiconductor substrate; etching the insulator to suspend the wide-bandgap layer; growing a compositionally-graded channel shell over the wide-bandgap layer; forming a gate structure forming spacers on the sidewalls of the gate structure; and forming a doped raised source drain region adjacent to the spacers.

Abstract: A semiconductor device comprising a suspended semiconductor nanowire inner gate and outer gate. A first epitaxial dielectric layer surrounds a nanowire inner gate. The first epitaxial dielectric layer is surrounded by an epitaxial semiconductor channel. The epitaxial semiconductor channel surrounds a second dielectric layer. A gate conductor surrounds the second dielectric layer. The gate conductor is patterned into a gate line and defines a channel region overlapping the gate line. The semiconductor device contains source and drain regions adjacent to the gate line.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

Abstract: Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.

Abstract: A structure and method for forming a substrate, a buffer layer disposed on the substrate, an oxide layer disposed on the buffer layer, and a fin comprising a semiconductor material disposed on the oxide layer.

Abstract: Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: A method includes steps of: receiving a first energy and a second energy emitted from within close proximity to a computer; powering a portable unit using the first energy; determining a position and status of the portable unit using the second energy; and transmitting a user identifier from the portable unit to the computer for verification.

Abstract: An input device for use with a computer system includes: a pad and a portable unit operating as a computer mouse. The pad includes: a first antenna providing power to the portable unit, a radio frequency transmitter, a radio frequency receiver, a data link between the pad and the computer system, and an array of radio frequency antennas used for tracking a location of the portable unit. The portable unit includes at least one mouse antenna reflecting the radio frequency signals from the pad. The reflected radio frequency signals are used to estimate a location of the portable unit with respect to the array of radio frequency antennas in the pad.

Abstract: A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire.

Abstract: An upside-down p-FET is provided on a donor substrate. The upside-down p-FET includes: self-terminating e-SiGe source and drain regions; a cap of self-aligning silicide/germanide over the e-SiGe source and drain regions; a silicon channel region connecting the e-SiGe source and drain regions; buried oxide above the silicon channel region; and a gate controlling current flow from the e-SiGe source region to the e-SiGe drain region.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate stack around a portion of the nanowire, forming a capping layer on the gate stack, forming a spacer adjacent to sidewalls of the gate stack and around portions of nanowire extending from the gate stack, forming a hardmask layer on the capping layer and the first spacer, forming a metallic layer over the exposed portions of the device, depositing a conductive material over the metallic layer, removing the hardmask layer from the gate stack, and removing portions of the conductive material to define a source region contact and a drain region contact.

Abstract: A system is provided and includes a wafer and a mask. The wafer includes a silicon-on-insulator (SOI) structure disposed on a buried oxide (BOX) layer and has a first region with a first SOI thickness and a second region with a second SOI thickness, the first and second SOI thicknesses being different from one another and sufficiently large such that respective pairs of SOI pads connected via respective nanowires with different thicknesses are formable therein. The mask covers one of the first and second regions and prevents a thickness change of the other of the first and second regions from having effect at the one of the first and second regions.

Abstract: A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.