Abstract: The backside illuminated image sensor comprises a substrate of semiconductor material, detector elements arranged at a main surface, a dielectric layer on or above the main surface, a first capacitor layer and a second capacitor layer above the main surface, the capacitor layers forming a capacitor (C1, C2). A peripheral circuit is integrated in the substrate apart from the detector elements, the peripheral circuit being configured for one or more operations of the group consisting of voltage regulation, charge pump operation and stabilization of clock generation, and the capacitor layers are electrically connected with contact regions of the peripheral circuit.

Abstract: The semiconductor device comprises a substrate of semiconductor material having a main surface, an integrated circuit in the substrate, a photodetector element or array of photodetector elements arranged at or above the main surface, and at least one nanomaterial film arranged above the main surface. At least part of the nanomaterial film has a scintillating property. The method of production includes the use of a solvent to apply the nanomaterial film, in particular by inject printing, by silk-screen printing, by spin coating or by spray coating.

Abstract: An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer ?2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

Abstract: An image sensor comprises an array of pixels comprising: a pinned photodiode; a first sense node A; a second sense node B; a transfer gate TX connected between the pinned photodiode and the first sense node A; a first reset transistor M3 connected between a voltage reference line Vrst and the second sense node B; a second reset transistor M4 connected between the first sense node A and the second sense node B; and a buffer amplifier M1 having an input connected to the first sense node A. The control logic is arranged to operate the pixels in a low conversion gain mode and in a high conversion gain mode. In each of the conversion gain modes the control logic is arranged to operate one of a first reset control line RS1 and a second reset control line RS2 to continuously switch on one of the first reset transistor M3 and the second reset transistor M4 during a readout period of an operational cycle of the pixels.

Abstract: An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer?2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

Abstract: An image sensor comprises a first die with an array of pixels and a second die. The first die and second die are stacked together. A first in-pixel part of an analog-to-digital converter (ADC) outputs at least one current signal. The first in-pixel part of the ADC is a Differential Transconductance Amplifier includes a first differential input for receiving the analog signal and a second differential input for receiving a reference signal. There is at least one output bus connected between the first in-pixel part of the ADC on the first die and the second part of the ADC on the second die. The first part of the ADC is adapted to output the at least one current signal to the at least one output bus, and the second part of the ADC is adapted to receive the at least one current signal and to generate a digital signal.

Abstract: A pixel structure comprises an epitaxial layer (1) of a first conductivity type. A photo-sensitive element comprises a first region (4) of a second conductivity type and a second region (3) of the first conductivity type positioned between the epitaxial layer (1) and the first region (4). A charge storage node (ø2) is arranged to store charges acquired by the photo-sensitive element, or to form part of a charge storage element. A third region (2) of the second conductivity type is positioned between the charge storage node and the epitaxial layer. The pixel structure further comprises a charge-to-voltage conversion element (13) for converting charges from the charge storage node to a voltage signal and an output circuit (21, 22) for selectively outputting the voltage signal from the pixel structure.

Abstract: A pixel array includes a plurality of pixel structures, with each pixel structure having a photo-sensitive element for generating charge in response to incident light; a charge conversion element; a first transfer gate and a second transfer gate connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a supply line; and an output stage. A first transfer gate control line is connected to the first transfer gates of a first sub-set of the pixel structures in the array; and a second transfer gate control line connected to the second transfer gates of a second sub-set of the pixel structures in the array. The first sub-set of pixel structures and second sub-set of pixel structures partially overlap, having at least one pixel structure in common between them.

Abstract: An image sensor comprises a first die with an array of pixels and a second die. The first die and second die are stacked together. A first in-pixel part of an analog-to-digital converter (ADC) outputs at least one current signal. The first in-pixel part of the ADC is a Differential Transconductance Amplifier includes a first differential input for receiving the analog signal and a second differential input for receiving a reference signal. There is at least one output bus connected between the first in-pixel part of the ADC on the first die and the second part of the ADC on the second die. The first part of the ADC is adapted to output the at least one current signal to the at least one output bus, and the second part of the ADC is adapted to receive the at least one current signal and to generate a digital signal.

Abstract: An image sensor comprises an array of pixels comprising: a pinned photodiode; a first sense node A; a second sense node B; a transfer gate TX connected between the pinned photodiode and the first sense node A; a first reset transistor M3 connected between a voltage reference line Vrst and the second sense node B; a second reset transistor M4 connected between the first sense node A and the second sense node B; and a buffer amplifier M1 having an input connected to the first sense node A. The control logic is arranged to operate the pixels in a low conversion gain mode and in a high conversion gain mode. In each of the conversion gain modes the control logic is arranged to operate one of a first reset control line RS1 and a second reset control line RS2 to continuously switch on one of the first reset transistor M3 and the second reset transistor M4 during a readout period of an operational cycle of the pixels.

Abstract: A pixel array for imaging comprises an array of pixels of a first pixel type and a second pixel type. Each pixel of the first pixel type comprises a first photo-sensitive element having a first area. Each pixel of the second pixel type comprises a second photo-sensitive element and a third photo-sensitive element. The second photo-sensitive element has a second area, which is smaller than the first area. Only the second photo-sensitive element in the pixel of the second pixel type is connected to a readout circuit. The third photo-sensitive element is connected to a charge drain via a permanent connection or a switchable connection. Outputs of the second photo-sensitive elements can be used to perform phase detect autofocussing.

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure.

Abstract: A pixel comprises a pinned photodiode for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the pinned photodiode and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage.

Abstract: A pixel structure comprises an epitaxial layer (1) of a first conductivity type. A photo-sensitive element comprises a first region (4) of a second conductivity type and a second region (3) of the first conductivity type positioned between the epitaxial layer (1) and the first region (4). A charge storage node (ø2) is arranged to store charges acquired by the photo-sensitive element, or to form part of a charge storage element. A third region (2) of the second conductivity type is positioned between the charge storage node and the epitaxial layer. The pixel structure further comprises a charge-to-voltage conversion element (13) for converting charges from the charge storage node to a voltage signal and an output circuit (21, 22) for selectively outputting the voltage signal from the pixel structure.

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

Abstract: A pixel array for imaging comprises an array of pixels of a first pixel type and a second pixel type. Each pixel of the first pixel type comprises a first photo-sensitive element having a first area. Each pixel of the second pixel type comprises a second photo-sensitive element and a third photo-sensitive element. The second photo-sensitive element has a second area, which is smaller than the first area. Only the second photo-sensitive element in the pixel of the second pixel type is connected to a readout circuit. The third photo-sensitive element is connected to a charge drain via a permanent connection or a switchable connection. Outputs of the second photo-sensitive elements can be used to perform phase detect autofocussing.

Abstract: A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

Abstract: A pixel array includes a plurality of pixel structures, with each pixel structure having a photo-sensitive element for generating charge in response to incident light; a charge conversion element; a first transfer gate and a second transfer gate connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a supply line; and an output stage. A first transfer gate control line is connected to the first transfer gates of a first sub-set of the pixel structures in the array; and a second transfer gate control line connected to the second transfer gates of a second sub-set of the pixel structures in the array. The first sub-set of pixel structures and second sub-set of pixel structures partially overlap, having at least one pixel structure in common between them.