Abstract: A pixel array comprises a plurality of photo-sensitive elements arranged in rows and columns and readout circuitry for reading a value of a photo-sensitive element. Shared readout circuitry is provided for a pair of adjacent photo-sensitive elements. Adjacent instances of the shared readout circuitry are staggered with respect to one another. For a layout having shared readout circuitry for a pair of photo-sensitive elements, adjacent instances of the shared readout circuitry are offset by a horizontal distance of one column and a vertical distance of one row of the array. The shared readout circuitry can serve a pair of adjacent photo-sensitive elements in a row or column of the array, or a pair of photo-sensitive elements which are diagonally adjacent in the array. An improved yield and symmetry results from staggering instances of the shared readout circuitry.

Abstract: A method of manufacturing a backside illuminated image sensor includes providing a start material that has a layer of semiconductor material on a substrate. The layer of semiconductor material has a first face and a second, backside, face. The layer of semiconductor material is processed to form semiconductor devices in the layer adjacent the first face. At least a part of the substrate is removed to leave an exposed face. A passivation layer is formed on the exposed face, the passivation layer having negative fixed charges. The passivation layer can be Al2O3 (Sapphire). The passivation layer can have a thickness less than 5 ?m, advantageously less than 1 ?m, and more advantageously in the range 1 nm-150 nm. Another layer, or layers, can be provided on the passivation layer, including: an anti-reflective layer, a layer to improve passivation, a layer including a color filter pattern, a layer comprising a microlens.

Abstract: An array of active pixels comprises rows of pixels and row select lines for selecting rows of pixels. Each active pixel comprises a buffer amplifier for buffering an output of a photo-sensitive element. An output of the buffer amplifier can be selectively put into a high impedance state, by control of the input of the buffer amplifier, when there is a defect in the row select line for that pixel. This allows other rows, which are defect-free, to remain operating as normal. A disable line can be provided for a row of pixels and each pixel can have a switch connected to the disable line. Alternatively, a first supply line powers a row of pixels. Each pixel comprises a reset switch connected between a photo-sensitive element and the first supply line for resetting the photo-sensitive element.

Abstract: A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

Abstract: A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure.

Abstract: A method of manufacturing a backside illuminated image sensor includes providing a start material that has a layer of semiconductor material on a substrate. The layer of semiconductor material has a first face and a second, backside, face. The layer of semiconductor material is processed to form semiconductor devices in the layer adjacent the first face. At least a part of the substrate is removed to leave an exposed face. A passivation layer is formed on the exposed face, the passivation layer having negative fixed charges. The passivation layer can be Al2O3 (Sapphire). The passivation layer can have a thickness less than 5 ?m, advantageously less than 1 ?m, and more advantageously in the range 1 nm-150 nm. Another layer, or layers, can be provided on the passivation layer, including: an anti-reflective layer, a layer to improve passivation, a layer including a color filter pattern, a layer comprising a microlens.

Abstract: An analogue-to-digital (A/D) converter converts an analogue input signal to a digital code representing the analogue input signal. The A/D converter includes a comparator for comparing the input signal with a reference signal, a search logic block for determining the digital code, and an A/D converter arranged for receiving input from the search logic block and for providing the reference signal to be applied to the comparator. At least a first portion of the A/D converter is implemented with equal capacitors and may be controlled by a thermometer coded signal. Additionally, the A/D converter may include a second portion implemented using binary weighted capacitors controlled by a thermometer coded or binary coded signal. The A/D converter may also include a plurality of A/D converters coupled by an analogue addition circuit or a weighted summing amplifier.

Abstract: A pixel array comprises a plurality of photo-sensitive elements arranged in rows and columns and readout circuitry for reading a value of a photo-sensitive element. Shared readout circuitry is provided for a pair of adjacent photo-sensitive elements. Adjacent instances of the shared readout circuitry are staggered with respect to one another. For a layout having shared readout circuitry for a pair of photo-sensitive elements, adjacent instances of the shared readout circuitry are offset by a horizontal distance of one column and a vertical distance of one row of the array. The shared readout circuitry can serve a pair of adjacent photo-sensitive elements in a row or column of the array, or a pair of photo-sensitive elements which are diagonally adjacent in the array. An improved yield and symmetry results from staggering instances of the shared readout circuitry.

Abstract: A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Abstract: A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

Abstract: A system and method for estimating remaining run-time of an autonomous system by indirect measure is disclosed. In one aspect, the system includes a load circuit, an energy storage system (ESS) and an energy storage management system (ESM). The load circuit includes functional blocks. The ESS stores electric energy and is connected to the load circuit and configured to supply the varying electric current to the load circuit. The ESM is configured to estimate a remaining run-time of the autonomous system. The ESM includes an input connected to one of the functional blocks of the load circuit from which a first parameter being an indirect measure for the varying electric current supplied from the energy storage system to the load circuit is received. The ESM determines the remaining run-time from this first parameter.

Abstract: An array of active pixels comprises rows of pixels and row select lines for selecting rows of pixels. Each active pixel comprises a buffer amplifier for buffering an output of a photo-sensitive element. An output of the buffer amplifier can be selectively put into a high impedance state, by control of the input of the buffer amplifier, when there is a defect in the row select line for that pixel. This allows other rows, which are defect-free, to remain operating as normal. A disable line can be provided for a row of pixels and each pixel can have a switch connected to the disable line. Alternatively, a first supply line powers a row of pixels. Each pixel comprises a reset switch connected between a photo-sensitive element and the first supply line for resetting the photo-sensitive element.

Abstract: The present disclosure is related to an analogue-to-digital (A/D) converter (1) for converting an input signal (Vin) to a digital code representing said input signal. The A/D converter comprises a comparator (3) for comparing the input signal with a reference signal (VA), a search logic block (4) for determining the digital code and a digital-to-analogue converter (5) arranged for receiving input from the search logic block and for providing the reference signal to be applied to the comparator. The digital-to-analogue converter comprises at least a first portion implemented with equal capacitors (20). The ADC optionally further comprises a second portion implemented with binary weighted capacitors. The first portion is arranged for being controlled by a thermometer coded signal. The converter avoids charging-discharging of large capacitors during the search and therefore reduces the lost energy.

Abstract: An electronic power conversion circuit is presented for converting an input power to an output power. The circuit comprises at least one conversion block and a clock generator. Each conversion block comprises an input, an output and a plurality of charge storage elements and switches between the input and output. Each block is alternately switchable between a first state in which electric charge is loaded from the input and a second state in which electric charge is supplied as converted power to the output. The clock generator generates clock signals for controlling the switches and thereby switches between the first and second states. The circuit is characterized in that the clock generator comprises at least one input node for receiving at least one input parameter and in that the clock generator is provided for varying the frequency of the clock signals in relation to the at least one input parameter.

Abstract: A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Abstract: A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Abstract: The present invention discloses an amplifying circuit, comprising an amplifying element with at least an input terminal and an output terminal. A signal input node is provided, the signal levels of which at least two moments in time are to be amplified by the amplifying element. At least two connecting lines are provided between the signal input node and the amplifying element, for transferring a signal from the signal input node to the input terminal of the amplifying element. A memory element is located on at least one of the connecting lines, for storing a signal level of the signal input node at a moment in time, and a switching element is disposed on each connecting line, between the memory element and the input terminal of the amplifying element if a memory element is provided on the connecting line, for consecutively connecting signal levels of the signal input node at different moments in time to the same amplifying element.

Abstract: A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organised in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Abstract: The invention is a method for determining at least two corrected color values for a pixel, said pixel being embedded in a configuration of pixels and having a color filter for filtering substantially one color type while obtaining a measurement on the pixel. The method comprises the steps of measuring at least one signal on said pixel; transforming the measured signal into a representation having at least a luminance and a chrominance part; and transforming said representation into a color space representation of said pixel, said pixel having at least two color values in said color space representation.

Abstract: A multiplexing circuit for use in imaging devices is described comprising a series of signal input nodes, a series of first memory elements for storing a signal level on the corresponding signal input nodes and at least a first output node comprising a second memory element. A series of first switching elements is provided, each first switching element being connected to a first memory element on one side and a first output node on the other side, and a second switching element is provided to bring the first output node in a known state. The readout requires less energy consumption than known methods using amplifiers. The signal levels stored on the first memory elements may be outputs from pixels which may be formed in an array of columns and rows. The signal levels from different pixels may be combined together to improve signal to noise ratios.