Abstract: A nanowire structure that includes a conductive layer; conductive wires having first ends that contact the conductive layer and second ends that protrude from the conductive layer; and a lateral bridge layer that connects laterally a number of the conductive wires to provide a substantially uniform spacing between the conductive wires.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Abstract: A nanowire structure is manufactured by forming islands of conductive material on a substrate, and a conductive sacrificial layer in the space between conductive islands. The conductive islands include an anodic etch barrier layer. An anodizable layer is formed, over the conductive islands and sacrificial layer, and anodized to form a porous template. Nanowires are formed in regions of the porous template that overlie the conductive islands. Removal of the porous template and sacrificial layer leaves a nanowire structure including isolated groups of nanowires connected to respective conductive islands which function as current collectors. Respective stacks of conductive and insulator layers are formed over different groups of the nanowires to form respective capacitors that are electrically isolated from one another. A monolithic component may thus be formed including an array of isolated capacitors formed over nanowires.

Abstract: A porous region structure and a method of fabrication thereof are disclosed. The porous region structure is characterized by having a hard mask interface region with non-uniform pores sealed and thereby excluded functionally from the structure. The sealing of the hard mask interface region is done using a hard mask deposited on top of an anodization hard mask used to define the porous region of the structure. By excluding the hard mask interface region, the porosity ratio and the equivalent specific surface of the porous region structure can be controlled or quantified with higher accuracy. Corrosion due to exposure of an underlying metal layer of the structure is also significantly reduced by sealing the hard mask interface region.

Abstract: Three-dimensional capacitive structures may be produced by forming a capacitive stack conformally over pores in a region of porous anodic oxide. The porous anodic oxide region is provided on a stack of electrically-conductive layers including an anodization-resistant layer and an interconnection layer. In the pores there is a position having restricted diameter quite close to the pore bottom. In a first percentage of the pores in the region of anodic oxide, a functional portion of the capacitive stack is formed so as to extend into the pores no further than the restricted-diameter position. Cracks that may be present in the anodization-resistant layer have reduced effect on the properties of the capacitive structure. Increased thickness of the anodization-resistant layer can be tolerated, enabling equivalent series resistance of the overall capacitive structure to be reduced.

Abstract: A structure that includes: an insulating layer; a first metal layer above a first portion of the insulating layer; a first porous region of anodic oxide, above and in contact with the first metal layer; and a second porous region of anodic oxide, surrounding the first porous region, in contact with a second portion of the insulating layer adjacent to the first portion of the insulating layer, and in contact with the first metal layer, the second porous region forming an insulating region.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Abstract: A nanowire structure that includes a conductive layer; conductive wires having first ends that contact the conductive layer and second ends that protrude from the conductive layer; and a lateral bridge layer that connects laterally a number of the conductive wires to provide a substantially uniform spacing between the conductive wires.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Abstract: A porous region structure and a method of fabrication thereof are disclosed. The porous region structure is characterized by having a hard mask interface region with non-uniform pores sealed and thereby excluded functionally from the structure. The sealing of the hard mask interface region is done using a hard mask deposited on top of an anodization hard mask used to define the porous region of the structure. By excluding the hard mask interface region, the porosity ratio and the equivalent specific surface of the porous region structure can be controlled or quantified with higher accuracy. Corrosion due to exposure of an underlying metal layer of the structure is also significantly reduced by sealing the hard mask interface region.

Abstract: A semiconductor device that includes a porous anodic region for embedding a structure. The porous anodic region is defined by a ductile hard mask. The ductility of the hard mask reduces the potential for the hard mask to crack during the formation by anodization of the porous anodic region. The ductile hard mask may be a metal. The metal may be selected to form a stable oxide when exposed to the anodization electrolyte thereby enabling the hard mask to self-repair if a crack occurs during the anodization process.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Abstract: A Metal-Insulator-Metal type capacitor structure (1) comprising a substrate (2), a first electrically insulating layer (14) placed on the substrate (2), a lower electrode (6) placed on the first insulating layer (14), a layer of structured metal (12) comprising a plurality of pores disposed on the lower electrode (6), a MIM capacitor (4) comprising a first conductive layer (18) placed on the structured metal layer (12) in contact with the lower electrode (6) and inside the pores, a dielectric layer (20) covering the first conductive layer (18), a second conductive layer (24) covering the dielectric layer (20) in contact with an upper electrode (8) placed on the MIM capacitor (4) and a second electrically insulating layer (16) placed on the upper electrode (8).

Abstract: A Metal-Insulator-Metal type capacitor structure (1) comprising a substrate (2), a first electrically insulating layer (14) placed on the substrate (2), a lower electrode (6) placed on the first insulating layer (14), a layer of structured metal (12) comprising a plurality of pores disposed on the lower electrode (6), a MIM capacitor (4) comprising a first conductive layer (18) placed on the structured metal layer (12) in contact with the lower electrode (6) and inside the pores, a dielectric layer (20) covering the first conductive layer (18), a second conductive layer (24) covering the dielectric layer (20) in contact with an upper electrode (8) placed on the MIM capacitor (4) and a second electrically insulating layer (16) placed on the upper electrode (8).

Abstract: A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.

Abstract: An integrated circuit includes at least one interconnection level and an acoustic resonator provided with an active element and a support. The includes at least one bilayer assembly having a layer of high acoustic impedance material and a layer of low acoustic impedance material. The support further includes a protruding element arranged on a metallization level of the interconnection level, making it possible to produce an electrical contact between an interconnection level and the active element of the acoustic resonator.

Abstract: The arrays of independently-addressable resistors are commonly used to control miniature elements. The invention proposes solving the problem caused by the loss of power dissipated in the addressed resistor by choosing, for this resistor, a material with a negative thermal coefficient resistance, which enables the addressing output of this resistor to be increased.

Abstract: The arrays of independently-addressable resistors are commonly used to control miniature elements. The invention proposes solving the problem caused by the loss of power dissipated in the addressed resistor by choosing, for this resistor, a material with a negative thermal coefficient resistance, which enables the addressing output of this resistor to be increased. A production method is also described.

Abstract: An integrated circuit includes at least one interconnection level and an acoustic resonator provided with an active element and a support. The includes at least one bilayer assembly having a layer of high acoustic impedance material and a layer of low acoustic impedance material. The support further includes a protruding element arranged on a metallization level of the interconnection level, making it possible to produce an electrical contact between an interconnection level and the active element of the acoustic resonator.

Abstract: A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.