Patents by Inventor Guy Parat

Guy Parat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060252229
    Abstract: A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.
    Type: Application
    Filed: June 23, 2004
    Publication date: November 9, 2006
    Inventors: Jean-Pierre Joly, Laurent Ulmer, Guy Parat
  • Patent number: 6435733
    Abstract: Assembly allowing for connection of optical fibres with optical or optoelectronic components and process for manufacturing this assembly. According to the invention, at least one fibre support (4, 6) is formed including, for each fibre (2), a V-shaped housing. The support and the component (32) are attached to a substrate (12) with meltable elements (16, 38) and the fibre is positioned in the housing so as to vertically align the fibre with the component, horizontal alignment being obtained by the melted elements. Application is to microelectronics.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: August 20, 2002
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Guy Parat, Patrice Caillat, Christiane Puget
  • Patent number: 5636683
    Abstract: A heating device is provided for connecting by means of a melting material to a connection support at least one component mounted on the support in at least one connection region at the periphery of the support. The device locally heats the support and/or the component in the connection region. Particular utility for the present invention is found in the area of production of flat display screens, although other utilities are also contemplated.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: June 10, 1997
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Claude Massit, Gerard Nicolas, Guy Parat
  • Patent number: 5450206
    Abstract: A process for checking the conformity of hybridization balls present on a chip or a substrate and its implementation device are provided. The process includes positioning the hybridization balls of the electronic component or substrate near a strip transparent to a predetermined wavelength. The hybridization balls are partially flattened against the strip by positioning the electronic component or substrate at a previously defined distance from the transparent strip. The previously defined distance corresponds to a theoretical reference ball height less an acceptable deviation between the theoretical reference ball height and a minimum height of the hybridization balls. The partial flattening creates ball flats on the hybridization balls at the strip. The hybridization balls are illuminated with a light beam of the predetermined wavelength that is emitted through the strip. A portion of the light beam reflected back through the strip by the hybridization balls to be checked and is acquired.
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: September 12, 1995
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Patrice Caillat, Guy Parat, Gerard Nicolas
  • Patent number: 4766084
    Abstract: The invention relates to a process for producing an electric contact on a HgCdTe substrate having a P conductivity and application to the production of an N/P diode. For producing an N/P diode, an insulating layer deposited on the HgCdTe substrate is etched by ion bombardment through a first mask, so as to produce a first opening in said insulating layer. The mask is removed and the substrate covered by the insulating layer undergoes a heat treatment, so as to at least mitigate the P conductivity drop induced by the ion bombardment in a first portion of the substrate facing the first opening. This is followed by ion implantation in a second portion of the substrate through a second mask in order to produce an N conductivity portion. This second mask is removed and the insulating layer is etched through a third mask by ion bombardment in order to produce a second opening facing the second portion. After removing the third mask, conductive pads are produced in the first and second openings.
    Type: Grant
    Filed: September 16, 1987
    Date of Patent: August 23, 1988
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Cecile Bory, Jean-Louis O. Buffet, Guy Parat