Patents by Inventor Guy T. Blalock

Guy T. Blalock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7215838
    Abstract: Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing methods. The resistive heater is comprised of a heater region and a conductive path region formed together in a first mask count from a relatively high resistance material. A conductor formed from a relatively low resistance material is formed directly on the conductive path region in a second mask count. Thermo optic devices formed by these two mask count methods are also described.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Guy T. Blalock
  • Patent number: 7183220
    Abstract: A plasma etching method includes forming a polymer comprising carbon and a halogen over at least some internal surfaces of a plasma etch chamber. After forming the polymer, plasma etching is conducted using a gas which is effective to etch polymer from chamber internal surfaces. In one implementation, the gas has a hydrogen component effective to form a gaseous hydrogen halide from halogen liberated from the polymer. In one implementation, the gas comprises a carbon component effective to getter the halogen from the etched polymer. In another implementation, a plasma etching method includes positioning a semiconductor wafer on a wafer receiver within a plasma etch chamber. First plasma etching of material on the semiconductor wafer occurs with a gas comprising carbon and a halogen. A polymer comprising carbon and the halogen forms over at least some internal surfaces of the plasma etch chamber during the first plasma etching.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: February 27, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, David S. Becker, Kevin G. Donohoe
  • Patent number: 7173339
    Abstract: An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. The invention also includes semiconductor devices that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention. Specifically, the present invention includes semiconductor devices including doped silicon oxide structures with substantially vertical sidewalls and adjacent undoped silicon oxide or silicon nitride structures exposed adjacent the sidewall.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: February 6, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kei-Yu Ko, Li Li, Guy T. Blalock
  • Patent number: 7153769
    Abstract: A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first material. The first and second materials are of different compositions, and are proximate one another at an interface. The first and second materials as being proximate one another at the interface are capable of reacting with one another at some minimum reaction temperature when in an inert non-plasma atmosphere at a pressure. The interface is provided at a processing temperature which is at least 50° C. below the minimum reaction temperature, and is provided at the pressure. With the interface at the processing temperature and at the pressure, the substrate is exposed to a plasma effective to impart a reaction of the first material with the second material to form a reaction product third material of the first and second materials over the first material. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Guy T. Blalock
  • Patent number: 7129724
    Abstract: A plasma probe includes a substrate having substantially the same properties as those of a substrate to be processed, a bottom electrode layer located over the substrate and electrically isolated therefrom, a dielectric layer positioned over the bottom electrode layer including apertures through which one or more electrodes of the bottom electrode layer are exposed, and at least one upper electrode layer electrically isolated from the bottom electrode layer by way of the dielectric layer. Electrodes of the bottom and upper electrode layers may communicate with meters which may provide real-time data representative of one or more properties of a region of a plasma to which the electrodes are exposed. The plasma probe may be fabricated by forming the bottom electrode layer over the substrate and separately forming one or more upper electrode layers over a sacrificial substrate. These structures are assembled with the dielectric layer therebetween.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: October 31, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Guy T. Blalock
  • Patent number: 7119031
    Abstract: This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is formed over a semiconductor substrate. A photoresist footer-reducing fluid is provided within pores of the porous antireflective coating. A positive photoresist is formed over the porous antireflective coating having the fluid therein. The positive photoresist is patterned and developed to form a patterned photoresist layer, with the fluid within the pores being effective to reduce photoresist footing in the patterned photoresist layer than would otherwise occur in the absence of the fluid within the pores. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Gurtej S. Sandhu, Jon P. Daley
  • Patent number: 7120336
    Abstract: A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower cladding. Since upper surfaces of the resonator and waveguide are substantially coplanar, the aspect ratio, as between the waveguide and resonator in an area where the waveguide and resonator front one another, decreases thereby increasing the bandwidth of the resonator. The depression is formed by photomasking and etching the lower cladding before forming the resonator and waveguide. Pluralities of resonators are also taught that are formed in a plurality of depressions of the lower cladding. To decrease resonator bandwidth, waveguide(s) are formed in the depression(s) of the lower cladding while the resonator is formed on the surface. Thermo optic devices formed with these resonators are also taught.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Guy T. Blalock, Howard E. Rhodes
  • Patent number: 7115529
    Abstract: A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber effective to react with the first monolayer and form a second monolayer on the substrate which is different in composition from the first monolayer. The second monolayer includes components of the first monolayer and the second precursor. In one implementation, the first and second precursor flowings are successively repeated effective to form a mass of material on the substrate of the second monolayer composition. Additional and other implementations are contemplated.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Guy T. Blalock, Gurtej S. Sandhu
  • Patent number: 7115926
    Abstract: In one aspect, the invention includes an etching process, comprising: a) providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight); b) providing a second material over the first material; and c) etching the second material at a faster rate than the first material. In another aspect, the invention includes a capacitor forming method, comprising: a) forming a wordline over a substrate; b) defining a node proximate the wordline; c) forming an etch stop layer over the wordline, the etch stop layer comprising carbon; d) forming an insulative layer over the etch stop layer; e) etching through the insulative layer to the etch stop layer to form an opening through the insulative layer; and e) forming a capacitor construction comprising a storage node, dielectric layer and second electrode, at least a portion of the capacitor construction being within the opening.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventors: John T. Moore, Guy T. Blalock, Scott Jeffrey DeBoer
  • Patent number: 7097782
    Abstract: In certain implementations, methods and apparatus include an antenna assembly having at least two overlapping and movable surface microwave plasma antennas. The antennas have respective pluralities of microwave transmissive openings formed therethrough. At least some of the openings of the respective antennas overlap with at least some of the openings of another antenna, and form an effective plurality of microwave transmissive openings through the antenna assembly. Microwave energy is passed through the effective plurality of openings of the antenna assembly and to a flowing gas effective to form a surface microwave plasma onto a substrate received within the processing chamber. At least one of the antennas is moved relative to another of the antennas to change at least one of size and shape of the effective plurality of openings through the antenna assembly effective to modify microwave energy passed through the antenna assembly to the substrate.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 29, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Trung Tri Doan
  • Patent number: 7094690
    Abstract: A deposition method includes, at a first temperature, contacting a substrate with a surface activation agent and adsorbing a first layer over the substrate. At a second temperature greater than the first temperature, the first layer may be contacted with a first precursor, chemisorbing a second layer at least one monolayer thick over the substrate. The first layer may enhance a chemisorption rate of the first precursor compared to the substrate without the surface activation agent adsorbed thereon. One deposition apparatus includes a deposition chamber with a precursor gas dispenser in a contacting zone and a cooling gas dispenser in a cooling zone. A substrate chuck moves by linear translational motion from the contacting zone to the cooling zone. The substrate chuck includes a substrate lift that positions a deposition substrate at an elevation above a heated surface of the substrate chuck when dispensing a cooling gas or surface activation agent.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: August 22, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Garo J. Derderian, Guy T. Blalock, Terry L. Gilton
  • Patent number: 7091654
    Abstract: A method for fabricating field emitters from a conductive or semiconductive substrate. A layer of low work function material may be formed on the substrate. Emission tips that include such a low work function material may have improved performance. An etch mask appropriate for forming emission tips is patterned at desired locations over the substrate and any low work function material thereover. An anisotropic etch of at least the substrate is conducted to form vertical columns therefrom. A sacrificial layer may then be formed over the vertical columns. A facet etch of each vertical column forms an emission tip of the desired shape. If a sacrificial layer was formed over the vertical columns prior to formation of emission tips therefrom, the remaining material of the sacrificial layer may be utilized to facilitate the removal of any redeposition materials formed during the facet etch.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: August 15, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Sanh D. Tang, Zhaohui Huang
  • Patent number: 7049244
    Abstract: A process for controlling the plasma etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by (1) maintaining various portions of the etch chamber at elevated temperatures, and/ox (2) using an etch chemistry having a fluorohydrocarbon gas containing at least as many hydrogen atoms as fluorine atoms, preferably CH2F2 or CH3F.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: May 23, 2006
    Assignee: Micron Technology, Inc.
    Inventors: David S. Becker, Guy T. Blalock, Fred L. Roe
  • Patent number: 7037179
    Abstract: Methods and apparatuses for planarizing a microelectronic substrate. In one embodiment, a planarizing pad for mechanical or chemical-mechanical planarization includes a base section and a plurality of embedded sections. The base section has a planarizing surface, and the base section is composed of a first material. The embedded sections are arranged in a desired pattern of voids, and each embedded section has a top surface below the planarizing surface to define a plurality of voids in the base section. The embedded sections are composed of a second material that is selectively removable from the first material. A planarizing pad in accordance with an embodiment of the invention can be made by constructing the embedded sections in the base section and then removing a portion of the embedded sections from the base section. By removing only a portion of the embedded sections, this procedure creates the plurality of voids in the base section and leaves the remaining portions of the embedded sections.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: May 2, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Guy T. Blalock
  • Patent number: 7022618
    Abstract: In one implementation, an etching process includes forming a carbon containing material over a substrate and plasma etching at a temperature of at least 400° C. using a hydrogen or oxygen containing plasma. In one implementation, a plasma etching process includes forming openings in a masking layer over a substrate and etching material beneath the masking through the openings. The masking layer is removed and the substrate is plasma etched at a temperature of at least 400° C. In one implementation, an etching process includes forming a residue over the substrate during a first etching and subsequently plasma etching to remove the residue. In one implementation, a chemical vapor deposition process includes positioning a semiconductor substrate within a plasma enhanced chemical vapor deposition reactor, plasma etching using a first gas chemistry, depositing a material over the substrate within the reactor using a second gas chemistry.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Sujit Sharan, Gurtej S. Sandhu, Guy T. Blalock
  • Patent number: 7022605
    Abstract: A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber effective to react with the first monolayer and form a second monolayer on the substrate which is different in composition from the first monolayer. The second monolayer includes components of the first monolayer and the second precursor. In one implementation, the first and second precursor flowings are successively repeated effective to form a mass of material on the substrate of the second monolayer composition. Additional and other implementations are contemplated.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Guy T. Blalock, Gurtej S. Sandhu
  • Patent number: 7020365
    Abstract: Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing methods. The resistive heater is comprised of a heater region and a conductive path region formed together in a first mask count from a relatively high resistance material. A conductor formed from a relatively low resistance material is formed directly on the conductive path region in a second mask count. Thermo optic devices formed by these two mask count methods are also described.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: March 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Guy T. Blalock
  • Patent number: 7006746
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: February 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Publication number: 20050280426
    Abstract: A method for evaluating characteristics of a plasma or the effects of the plasma on a substrate includes introducing a plasma probe into a reaction chamber. The plasma probe may be introduced into the chamber with or without a substrate. The plasma probe is exposed to substantially the same conditions to which the substrate is, has been, or will be exposed. The plasma probe may include features that represent corresponding features on the substrate. One or more characteristics of the plasma, or its effects on the plasma probe, may be evaluated at one or more locations on the plasma probe.
    Type: Application
    Filed: July 27, 2005
    Publication date: December 22, 2005
    Inventor: Guy T. Blalock
  • Publication number: 20050270046
    Abstract: A plasma probe includes a substrate having substantially the same properties as those of a substrate to be processed, a bottom electrode layer located over the substrate and electrically isolated therefrom, a dielectric layer positioned over the bottom electrode layer including apertures through which one or more electrodes of the bottom electrode layer are exposed, and at least one upper electrode layer electrically isolated from the bottom electrode layer by way of the dielectric layer. Electrodes of the bottom and upper electrode layers may communicate with meters which may provide real-time data representative of one or more properties of a region of a plasma to which the electrodes are exposed. The plasma probe may be fabricated by forming the bottom electrode layer over the substrate and separately forming one or more upper electrode layers over a sacrificial substrate. These structures are assembled with the dielectric layer therebetween.
    Type: Application
    Filed: July 27, 2005
    Publication date: December 8, 2005
    Inventor: Guy T. Blalock