Patents by Inventor Guy Therien

Guy Therien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100162023
    Abstract: A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Inventors: Efraim ROTEM, Barnes Cooper, Guy Therien, Eliezer Weissmann, Anil Aggarwal
  • Publication number: 20100162006
    Abstract: According to some embodiments, a power budget allocation engine of a multi-component computer system may receive a power budget allocation adjustment request signal from a first component. Based on the received budget allocation adjustment request signal (and, in some embodiments, a component preference), the power budget allocation engine may determine whether to adjust a power budget allocation signal provided to the first component.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 24, 2010
    Inventors: Guy Therien, Murali Ramadoss, Gregory D. Kaine, Eric C. Samson, Venkatesh Ramani
  • Patent number: 7334082
    Abstract: A method and system to detect an occurrence of a predetermined event within the system, and change a power state of a hard drive (HD) in response to the event, are described. In one embodiment, in response to detecting consecutive HD reads have been satisfied by a non-volatile cache (NVC) of the HD, for at least a predetermined period of time, or detecting that a predetermined quantity of consecutive HD reads have been satisfied by the NVC, spinning down the HD. In an alternative embodiment, in response to detecting a predetermined number of HD data transactions have been serviced by the NVC or the HD, canceling a planned spinning down of the HD or spinning up the HD.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: February 19, 2008
    Assignee: Intel Corporation
    Inventors: Andrew S. Grover, Guy Therien, Brian A. Leete
  • Patent number: 7017060
    Abstract: A method for automatically transitioning a processor to another performance level in a demand-based system. One embodiment of the invention provides for the automatic adjustment of processor frequency while preserving system responsiveness. The performance-level policy algorithm detects increased processor utilization quickly enough that transition to a higher performance level is comparable to maximum system performance. The performance-level policy algorithm delays processor transition to a lower performance level so that quick reversals in demand do not precipitate unnecessary transitioning.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: March 21, 2006
    Assignee: Intel Corporation
    Inventors: Guy Therien, Michael Walz
  • Publication number: 20050288886
    Abstract: A method for managing thermal condition of a thermal zone that includes multiple thermally controllable components include determining thermal relationship between the components and reducing temperature of a first component by reducing thermal dissipation of a second component.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 29, 2005
    Inventors: Guy Therien, Robert Jackson
  • Publication number: 20050144377
    Abstract: A method and system to adjust a non-volatile cache associativity are described. In one embodiment, the method and system include determining a status of the system; and setting an associativity level of the non-volatile memory cache (NVC) of the system, based on that status of the system. In one embodiment, the non-volatile memory unit is a cache of the hard drive. Furthermore, in one embodiment, determining the status of the system includes determining whether the system is a mobile computer, and if so, determining whether the system is receiving power from a battery source or AC power from a wall outlet.
    Type: Application
    Filed: December 30, 2003
    Publication date: June 30, 2005
    Inventors: Andrew Grover, Guy Therien, Brian Leete
  • Publication number: 20020133729
    Abstract: A method for automatically transitioning a processor to another performance level in a demand-based system. The invention provides for the automatic adjustment of processor frequency while preserving system responsiveness. The performance-level policy algorithm of the present invention detects increased processor utilization quickly enough that transition to a higher performance level is comparable to maximum system performance. The performance-level policy algorithm of an embodiment of the present invention delays processor transition to a lower performance level so that quick reversals in demand do not precipitate unnecessary transitioning.
    Type: Application
    Filed: March 19, 2001
    Publication date: September 19, 2002
    Inventors: Guy Therien, Michael Walz